An addressable memory having: a buffer memory adapted for coupling to a bus; a random access memory coupled to the buffer memory; an internal clock; and, a logic network, coupled to the bus and configured to transferring data among the buffer memory, the random access memory and the...http://www.google.de/patents/US5822777?utm_source=gb-gplus-sharePatent US5822777 - Dual bus data storage system having an addressable memory with timer controller fault detection of data transfer between the memory and the buses 
