A digital and a multiplication method are described, which lead to an efficient architecture for a hardware implementation of digital FIR and IIR filters into FPGAs. The multiplications of input sample data and delayed sample data with filter coefficients are performed by addressing look-up tables in...http://www.google.de/patents/US7046723?utm_source=gb-gplus-sharePatent US7046723 - Digital filter and method for performing a multiplication based on a look-up table
