An over-clock deterrent mechanism of a chipset which comprises an over-clock detection circuit for detecting over-clocking of a system (processor) clock signal based on comparison of ratio of the system (processor) clock signal which is likely to be over-clocked and a fixed, stable reference clock signal...http://www.google.de/patents/US6535988?utm_source=gb-gplus-sharePatent US6535988 - System for detecting over-clocking uses a reference signal thereafter preventing over-clocking by reducing clock rate
