A processor capable of fetching and executing variable length instructions is described having instructions of at least two lengths. The processor operates in multiple modes. One of the modes restricts instructions that can be fetched and executed to the longer length instructions. An instruction cache...http://www.google.de/patents/US20060200686?utm_source=gb-gplus-sharePatent US20060200686 - Power saving methods and apparatus to selectively enable cache bits based on known processor state
