A synchronous memory device is provided in which a timing and control circuit (28) receives timing and control inputs. A row address buffer (38) and row decoders (40 and 42) operate to enable rows in plural memory sections (30, 32, 34, and 36). Column decoders (58, 60, 62, and 64) operate to enable columns...http://www.google.de/patents/US5386385?utm_source=gb-gplus-sharePatent US5386385 - Method and apparatus for preventing invalid operating modes and an application to synchronous memory devices
