A method for low latency access to the control space. A pipeline processor executes instructions in multiple stages including a decode stage, one or more execution, stages, and a writeback stage. A control space access instruction includes a first field containing a control register specifier and a second...http://www.google.de/patents/US6408381?utm_source=gb-gplus-sharePatent US6408381 - Mechanism for fast access to control space in a pipeline processor
