A compressed instruction format for a VLIW processor allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory....http://www.google.de/patents/US5826054?utm_source=gb-gplus-sharePatent US5826054 - Compressed Instruction format for use in a VLIW processor
