In a communications system (10), data is transferred from a physical interface section (64) and two processors, a receive processor (66) and a transmit processor (68). The data is transferred from the physical interface (64) to the receive processor (66) through a receive fifo (112). Data is transferred...http://www.google.de/patents/US4890254?utm_source=gb-gplus-sharePatent US4890254 - Clock disabling circuit
