Systems and methods for transient error recovery in pipelined reduced instruction set computer (RISC) processors prevent state changes based on the execution of an instruction until the execution of the instruction is validated. If a transient fault occurs causing an error to appear in an instruction...http://www.google.de/patents/US20010025338?utm_source=gb-gplus-sharePatent US20010025338 - Systems and methods for transient error recovery in reduced instruction set computer processors via instruction retry
