A semiconductor memory device capable of saving power supply voltage and power consumption without increasing the forming area of memory cell array by using MTCMOS technology. In writing data in a memory cell 50-21, a signal RE is turned "H" level, an NMOS 61-1 is turned off and a virtual ground line...http://www.google.de/patents/US6643173?utm_source=gb-gplus-sharePatent US6643173 - Semiconductor memory device operating in low power supply voltage and low power consumption
