Very fast integrated OPL circuits, such as pseudo-NMOS OPL and dynamic OPL, comprising CMOS gate arrays having ultra-thin vertical NMOS transistors are disclosed. The ultra-thin vertical NMOS transistors of the CMOS gate arrays are formed with relaxed silicon germanium (SiGe) body regions with graded...http://www.google.de/patents/US20030227072?utm_source=gb-gplus-sharePatent US20030227072 - Output prediction logic circuits with ultra-thin vertical transistors and methods of formation
