A method and structure for controlling the timing of an access to a DRAM array in response to a row access (RAS#) signal and the rising and/or falling edges of a clock signal. Row address decoding and the deactivation of equalization circuits are initiated when the row access signal is received...http://www.google.de/patents/US5708624?utm_source=gb-gplus-sharePatent US5708624 - Method and structure for controlling internal operations of a DRAM array
