A microprocessor system includes a high speed primary bus, a plurality of master devices coupled to the high speed primary bus, and a plurality of peripherals coupled to the high speed primary bus. The peripherals include at least one memory. An arbiter circuit is coupled to the high speed primary bus...http://www.google.de/patents/US7203781?utm_source=gb-gplus-sharePatent US7203781 - Bus architecture with primary bus and secondary or slave bus wherein transfer via DMA is in single transfer phase engagement of primary bus
