A method is comprised of translating a bit stream defining the state of switches of an FPGA into a set of via geometries, or generating the set of via geometries directly from a physical design system. The via geometries are used to produce at least one via mask. The via mask is then used in a manufacturing...http://www.google.de/patents/US20030042930?utm_source=gb-gplus-sharePatent US20030042930 - Programmable gate array based on configurable metal interconnect vias
