A cache-coherent, multiple-bus, multiprocessing system and method interconnects multiple system buses and an I/O bus to a shared main memory and efficiently maintains cache coherency while minimizing the impact to latency and total bandwidth within the system. The system provides coherency filters which...http://www.google.de/patents/US5897656?utm_source=gb-gplus-sharePatent US5897656 - System and method for maintaining memory coherency in a computer system having multiple system buses
