A method for performing integrated section-level and full-chip timing verification is employed for integrated circuit designs that include several section designs. A plurality of bristle timing parameters define timing relationships between the section designs. A section-level verification procedure...http://www.google.de/patents/US5546320?utm_source=gb-gplus-sharePatent US5546320 - Method for performing integrated section-level and full-chip timing verification for custom microprocessor designs
