Mechanisms for generating a worst case current waveform for testing of integrated circuit devices are provided. Architectural analysis of an integrated circuit device is first performed to determine an initial worst case power workload to be applied to the integrated circuit device. Thereafter, the derived...http://www.google.de/patents/US7917347?utm_source=gb-gplus-sharePatent US7917347 - Generating a worst case current waveform for testing of integrated circuit devices
