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US006790727B2
(12) United States Patent ao) Patent No.: us 6,790,727 B2
Jones, Jr. et al. (45) Date of Patent: Sep. 14,2004
(54) INTEGRATION OF TWO MEMORY TYPES ON THE SAME INTEGRATED CIRCUIT
(75) Inventors: Robert E. Jones, Jr., Austin, TX (US);
Bruce E. White, Jr., Round Rock, TX
(US)
(73) Assignee: Freescale Semiconductor, Inc., Austin, TX (US)
( * ) Notice: Subject to any disclaimer, the term ol this patent is extended or adjusted under 35 U.S.C. 154(b) by 8 days.
(21) Appl. No.: 10/348,267
(22) Filed: Jan. 21, 2003
(65) Prior Publication Data
US 2003/0132500 Al Jul. 17, 2003
Related U.S. Application Data
(62) Division ol application No. 09/881,332, filed on Jun. 15, 2001, now Pat. No. 6,531,731.
(51) Int. CI.7 H01L 21/336
(52) U.S. CI 438/257; 438/591; 438/981;
257/314; 257/315; 257/411
(58) Field of Search 438/257, 591,
438/260-261, 287-288, 593, 981; 257/410-411,
314-316
(56) References Cited
U.S. PATENT DOCUMENTS
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6,083,791 A * 7/2000 Bergemont 438/258
6,146,948 A * 11/2000 Wu et al 438/275
6,265,739 Bl 7/2001 Yaegashi
6,300,193 Bl 10/2001 Forbes
6,310,376 Bl * 10/2001 Ueda et al 257/315
6,320,784 Bl 11/2001 Muralidhar
6,351,411 B2 2/2002 Forbes
6,642,105 B2 * 11/2003 Kim et al 438/257
2001/0016388 Al * 8/2001 Koyama et al 438/275
FOREIGN PATENT DOCUMENTS
GB 2054956 A 2/1981
JP 10092957 A * 4/1998 H01L/21/8247
OTHER PUBLICATIONS
Tiwari et al., "Technology and Power-Speed Trade-Offs in Quantum-dot and Nano-crystal Memory Devices," 1997 Symposium on VLSI Technology Digest ol Technical Papers, pp. 133-134.
* cited by examiner
Primary Examiner—-Jerome Jackson
Assistant Examiner—Jose R. Diaz
(74) Attorney, Agent, or Firm—James L. Clingan, Jr.
