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DIFFERENTIAL SIGNAL PROBE WITH
INTEGRAL BALUN
CROSS-REFERENCE TO RELATED
APPLICATIONS 5
This application claims the benefit of U.S. Provisional App. No. 60/812,150, filed Jun. 9, 2006.
BACKGROUND OF THE INVENTION 10
The present invention relates to probe measurement systems for testing integrated circuits and other microelectronic devices and, more particularly, probe measurement systems utilizing differential signals to test circuits and devices. 15
Integrated circuits (ICs) and other microelectronic devices are fabricated on the surface of a wafer or substrate and commonly utilize single ended or ground referenced signals that are referenced to a ground plane at the lower surface of the substrate on which the active and passive devices of the 20 circuit are fabricated. As a result of the physical make up of the devices of an integrated circuit, parasitic interconnections exist between many of the parts of the individual devices and between parts of the devices and the wafer on which the devices are fabricated. These interconnections are commonly 25 capacitive and/or inductive in nature and exhibit frequency dependent impedances. For example, the terminals of transistors fabricated on semi-conductive substrates or wafers are typically capacitively interconnected, through the substrate, to the ground plane and, at higher frequencies, the ground 30 potential and the true nature of ground referenced signals becomes uncertain. Balanced devices utilizing differential signals are more tolerant to poor radio frequency (RF) grounding than single ended devices making them increasingly attractive as ICs are operated at higher and higher fre- 35 quencies.
Referring to FIG. 1, a differential gain cell 20 is a balanced device comprising two nominally identical circuit halves 20A, 20B. When biased with direct current, for example, a current sourced from a DC current source 22, and stimulated 40 with a differential mode signal, comprising even and odd mode components of equal amplitude and opposite phase (S,+1 and S,-1), a virtual ground is established at the symmetrical axis 26 of the two circuit halves. At the virtual ground, the potential at the operating frequency does not 45 change with time regardless of the amplitude of the stimulating signal. The quality of the virtual ground of a balanced device is independent of the physical ground path enabling balanced or differential circuits to tolerate poor RF grounding better than circuits operated with single ended signals. In 50 addition, the two component waveforms of the differential output signal (S0+1 and S0_1) are mutual references enabling digital devices to operate faster, with greater certainty in transitioning from one binary value to the other and with a reduced voltage swing for the signal. Moreover, balanced or 55 differential circuits have good immunity to noise from external sources, such as adjacent conductors, because noise tends to couple, electrically and electromagnetically, in the common mode and cancel in the differential mode. The improved immunity to noise extends to even-harmonic frequencies 60 since signals that are of opposite phase at the fundamental frequency are in phase at the even harmonics.
Following fabrication of the ICs, the individual dies on which the ICs are fabricated are separated or singulated and encased in a package that provides for electrical connections 65 between the exterior of the package and the circuit on the enclosed die. The separation and packaging of a die com
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prises a significant portion of the cost of manufacturing a device that includes an IC and to monitor and control the IC fabrication process and avoid the cost of packaging defective dies, manufacturers commonly add electrical circuits or test structures to the wafer to enable on-wafer testing or "probing" to verify characteristics of elements of the integrated circuits before the dies are singulated. A test structure typically includes a device-under-test (DUT) 30, a plurality of metallic probe orbondpads 32 that are deposited at the wafer's surface and a plurality of conductive vias 34 that connect the bond pads to the DUT which is typically fabricated beneath the surface of the wafer with the same process that is used to fabricate the corresponding components of the marketable IC. The DUT typically comprises a simple circuit that includes a copy of one or more of the basic elements of the marketable integrated circuit, such as a single line of conducting material, a chain of vias or a single transistor. Since the circuit elements of the DUT are fabricated with the same process as the corresponding elements of the marketable integrated circuits, the electrical properties of the DUT are expected to be representative of the electrical properties of the corresponding components of the marketable integrated circuit.
The DUT of the test structure 40 comprises the differential gain cell 20, a common elemental device of balanced or differential circuitry. A differential gain cell has five terminals; four signal terminals and a bias terminal through which the transistors of the differential cell are biased. The four signal terminals comprise two input terminals to receive the even and odd mode components of the differential input signal from a signal source and two output terminals to transmit the even and odd mode components of the differential output signal for the differential gain cell to a signal sink. Two probes 42, 44 are commonly utilized when probing a test structure comprising a differential or balanced device. One probe typically conducts the signals from the signal source to the probe pads of the test structure and the second probe conducts the signals from the test structure to the signal sink. Typically, one of the two probes has at least three probe tips, in a signalground-signal arrangement, to conduct two of the differential signal components and to bias the transistors of the differential cell.
ICs are typically characterized "on-wafer" by applying a test instrument generated signal to the test structure and measuring the response of the test structure to the signal. Referring to FIG. 2, at higher frequencies, on-wafer characterization is commonly performed with a network analyzer 100. A network analyzer comprises a source 102 of an AC signal, often a radio frequency (RF) signal, that is used to stimulate the DUT 30 of a test structure. Directional couplers or bridges pick off the forward or reverse waves traveling to or from the test structure and direct them to a signal sink 104 where they are down-converted in intermediate frequency (IF) sections, filtered, amplified and digitized. The result of the signal processing in the network analyzer is a plurality of s-parameters (scattering parameters), the ratio of a normalized power wave comprising the response of the DUT to the normalized power wave comprising the stimulus supplied by the signal source, that register the response of the DUT to the stimulating signal. A forward-reverse switch 106 enables reversing the connections between the probe(s) and the network analyzer so that the respective pairs of probe pads receiving the input signal and transmitting the output signal can be reversed.
A four-port network analyzer is desirable when testing differential devices because it can output and receive differential signals enabling mixed mode analysis of the devices. However, four-port network analyzers are relatively uncom
