[54] METHOD FOR MANUFACTURING LCD
DEVICE CAPABLE OF AVOIDING SHORT
CIRCUIT BETWEEN SIGNAL LINE AND
PIXEL ELECTRODE
[75] Inventors: Seiichi Matsumoto; Osamu Sukegawa;
Wakahiko Kaneko; Hirofumi Ihara,
all ol Tokyo, Japan
[73] Assignee: NEC Corporation, Tokyo, Japan
[21] Appl. No.: 08/962,299 [22] Filed: Oct. 31, 1997
Related U.S. Application Data
[62] Division of application No. 08/364,221, Dec. 27, 1994, Pat. No. 5,872,021.
[30] Foreign Application Priority Data
Dec. 30, 1993 [JP] Japan 5-352442
[51] Int. CI.7 H01L 21/84; H01L 21/336;
G02F 1/136
[52] U.S. CI 438/30; 438/158; 438/159;
257/59
[58] Field of Search 257/59, 88; 438/30,
438/158, 159, FOR 155, FOR 183, FOR 200, FOR 261, FOR 211, FOR 208; 359/54,
55, 59
[56] References Cited
U.S. PATENT DOCUMENTS
5,032,531 7/1991 Tsutsui et al. .
5,075,244 12/1991 Sakai et al. .
5,166,086 11/1992 Takeda et al. .
5,483,082 1/1996 Takizawa et al 257/59
5,539,551 7/1996 Nomoto et al 359/59
5,818,551 10/1998 Park 349/43
5,824,564 10/1998 Watanabe 438/30
FOREIGN PATENT DOCUMENTS
64-24326 2/1989 Japan .
2-234126 9/1990 Japan .
4-324938 11/1992 Japan .
Primary Examiner—M. Wilczewski
Attorney, Agent, or Firm—Foley & Lardner
[57] ABSTRACT
In a method for manulacturing an LCD device where a gate insulating layer is formed on an insulating substrate and a signal line pattern layer and a pixel electrode pattern layer are formed on a signal line forming area and a pixel electrode forming area, respectively, of the gate insulating layer, a part of the gate insulating layer between the signal line forming area and the pixel electrode forming area is etched.
3 Claims, 21 Drawing Sheets
