[54] INTERFACE FOR USE BETWEEN A MEMORY AND COMPONENTS OF A MODULE SWITCHING APPARATUS
[75] Inventors: David L. Budde, Portland; David G.
Carson, Hillsboro; David B. Johnson, Portland; Doran K. Wilde, Aloha, all of Oreg.
[73] Assignee: Intel Corporation, Santa Clara, Calif. [21] Appl. No.: 336,866 [22] Filed: Jan. 4, 1982
[51] Int. C1.3 G06F 13/00
[52] U.S. CI 364/200
[58] Field of Search 364/200 MS File, 200,
364/900
[56] References Cited
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Primary Examiner—Gareth D. Shaw
Assistant Examiner—Jameson Lee
Attorney, Agent, or Firm—Owen L. Lamb
(MCU) modules (112). The matrix is composed of processor buses (105) and corresponding control lines; and memory buses (107) with corresponding control lines (108). At the intersection of these lines is a bus interface unit node (100). The bus interface units function to pass memory requests from a processor module to a memory module attached to an MCU node and to pass any data associated with the requests. The memory bus is a packet-oriented bus. Accesses are handled by means of a series of messages transmitted by message generator (417) in accordance with a specific control protocol. Packets comprising one or more bus transmission slots are issued sequentially and contiguously. Each slot in a packet includes an opcode, address, data, control, and parity-check bits. Write-request packets and readrequest packets are issued to the memory-control unit. The memory-control unit responds with reply packets. A message controller (416), bus monitor (413), and pipeline and reply monitor (414), run the memory bus in a three-level pipeline mode. There may be three outstanding requests in the bus pipeline. Any further requests must wait for a reply message to free-up a slot in the pipeline before proceeding. Request messages increase the length of the pipeline and reply messages decrease the length of a pipeline. A control message, called a blurb, does not affect the pipeline length and can be issued when the pipeline is not full. The different messages are distinguished by three control signals (405) that parallel the data portion of the bus. The message generator (417) and interface logic (404) drive these control lines to indicate the message type, the start and end of the message, and possible error conditions. The pipeline and reply monitor (414) and the message controller (416) cooperate to insert a reply to a particular request in the pipeline position corresponding to the particular request that invoked the reply.
8 Claims, 3 Drawing Figures
