Coordination of out-of-sequence fetching between multiple processors using ...

United States Patent [19]

Frey et al.

...

US005185871A

[ii] Patent Number: 5,185,871 [45] Date of Patent: Feb. 9, 1993

[54] COORDINATION OF OUT-OF-SEQUENCE FETCHING BETWEEN MULTIPLE PROCESSORS USING RE-EXECUTION OF INSTRUCTIONS

[75] Inventors: Bradly G. Frey, Boca Raton, Fla.;

Raymond J. Pedersen, Garrison,
N.Y.

[73] Assignee: International Business Machines
Corporation, Armonk, N.Y.

[21] Appl. No.: 457,222

[22] Filed: Dec. 26, 1989

[51] Int. CI.5 G06F 11/00; G06F 11/28

[52] U.S. a 395/375; 364/262.4;

364/262.9; 364/265.6; 364/DIG. 1; 364/944.6;

364/945.1

[58] Field of Search 395/800, 375

[56] References Cited

U.S. PATENT DOCUMENTS

3,781,814 12/1973 Deerfield 395/375

3,928,857 12/1975 Carter et al 395/250

4,521,851 6/1985 Trubisky et al 364/200

4,613,935 9/1986 Couleur 364/200

4,617,625 10/1986 Nagashima et al 364/200

4,682,281 7/1987 Voffinder et al 364/200

4,731,739 3/1988 Woffir.den et al 364/200

4,760,519 7/1988 Papworth et al 364/200

4,791,557 12/1988 Angel et al 364/200

4,872,111 10/1989 Daberkow et al 364/200

4,916,652 4/1990 Schwarz et al 364/748

4,991,090 3/1991 Emma et al 364/200

5,072.364 10/1991 Jardine et al 395/375

5,075,840 12/1991 Grohoski et al 395/800

Primary Examiner—Thomas C. Lee Assistant Examiner—Meng-Ai T. An

Attorney, Agent, or Firm—Bernard M. Goldman

[57] ABSTRACT

The disclosure describes means for allowing the sequencing of operand fetches to deviate from the conceptual sequence specified in the program. Allowing fetch sequencing deviations may improve system performance, while not causing any deviation in program execution results. Out-of-sequence (COS) fetching may be caused by issuing each fetch without regard to the following conditions: 1. a delay in issuance to storage (such as a delay in generating the address for a fetch request); 2. a speed up in operand data return (such as due to fetching the operand data from a store buffer in the execution unit without going to storage for the data); 3. a delay in the return of operand data (such as when a fetch request has a cache miss and its data must be obtained from the storage hierarchy); or 4. an overlap in the return of fetch data for a serializer instruction with execution of instructions preceding the serializer or data and instruction fetching for instructions following the serializer before its completion. Each fetch operand of a serializer is handled as OOS even when it is not OOS in order to eliminate serialized fetching. Operand store compare (OSC) cont/ols are provided to control an OOS fetch dependent on a conceptually prior store operand. If an OOS condition is detected that possibly may have caused wrong data, an execution retry occurs beginning with the currently incomplete instruction stream, and the retry may include OOS fetching. The integrity of data is maintained when an OOS fetch operand is exposed to a cross-invalidation (XI) hit by the storage request of another CPU in a multiprocessor (MP) system.

38 Claims, 16 Drawing Sheets