PC board having clustered blind vias

(54) PC BOARD HAVING CLUSTERED BLIND VIAS

(75) Inventor: Roy Henson, Pleasanton, CA (US)

(73) Assignee: FormFactor, Inc., Livermore, CA (US)

( * ) Notice: Subject to any disclaimer, the term ol this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.

(21) Appl. No.: 09/060,308

(22) Filed: Apr. 14, 1998

(51) Int. CI.7 H05K 1/11; H01R 12/04

(52) U.S. CI 174/262; 174/261

(58) Field of Search 174/261, 262,

174/263, 264, 265, 266; 361/780, 794,

781, 799

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* cited by examiner

Primary Examiner—Kamand Cuneo
Assistant Examiner—-Jeremy Norris

(74) Attorney, Agent, or Firm—Sterne, Kessler, Goldstein & Fox, PLLC

(57) ABSTRACT

A multilayer printed circuit board having clustered blind vias in power layers to lacilitate the routing ol signal traces in signal layers. A portion ol the blind vias in the power layers are grouped together to form a cluster ol blind vias. Corresponding signal routing channels are provided in the signal layers and aligned with the cluster ol blind vias in the power layers to permit routing ol signal traces or signal circuitry therethrough. A method ol manulacturing the multilayered printed circuit board includes assembling a first subassembly ol power layers, forming a group ol clustered power vias through the first subassembly, assembling a second subassembly ol signal layers, combining the first subassembly with the second subassembly such that the clustered vias in the first subassembly align with signal routing channels in the second subassembly, forming signal vias that extend through the first and second subassemblies, and seeding or plating the power and signal vias.

16 Claims, 10 Drawing Sheets