Multi-chip module packaging device using flip-chip bonding technology

(54) MULTI-CHIP MODULE PACKAGING DEVICE USING FLIP-CHIP BONDING TECHNOLOGY

(75) Inventor: Jen-Kuang Fang, Kaoshiung (TW)

(73) Assignee: Advanced Semiconductor Engineering, Inc. (TW)

( * ) Notice: Subject to any disclaimer, the term ol this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.

(21) Appl. No.: 10/282,637

(22) Filed: Oct. 29, 2002

(65) Prior Publication Data

US 2003/0094693 Al May 22, 2003 (30) Foreign Application Priority Data

Nov. 20, 2001 (TW) 90128736 A

(51) Int. CI.7 H01L 23/52; H01L 29/40

(52) U.S. CI 257/784; 527/723; 527/734

(58) Field of Search 257/690-696,

257/723, 724, 706, 707, 734, 738, 777, 778, 781, 784, 796, 779

(56) References Cited

U.S. PATENT DOCUMENTS

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5,811,317 A * 9/1998 Maheshwari et al 29/827

6,335,104 Bl * 1/2002 Sambucetti et al 428/615

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2003/0099767 Al * 5/2003 Fang 427/96

OTHER PUBLICATIONS

Peter Van Zant, Microchip Fabrication, 2000, McGraw-Hill, Fourth Edition, 572-573.*

Chales A. Harper, Electronic Packaging and Interconnection Handbook, McGraw-Hill, 2000, 1.24 and 1.25.*

* cited by examiner

Primary Examiner—Amir Zarabian
Assistant Examiner—Monica Lewis
(74) Attorney, Agent, or Firm—Seylarth Shaw LLP

(57) ABSTRACT

The present invention discloses a multi-chip module packaging device which has outward extension portions ol under bump metallurgies (UBM) for satislying the bonding area requirement during wire bonding operation. Therefore, chips have electrical connections with metal bonding wires welded on the extended portions for transmitting electrical signals between each other. That is, the number ol circuit layers ol the substrate used in the device can be reduced; lurthermore save on the production cost.

11 Claims, 3 Drawing Sheets