United States Patent  [li] Patent Number: 4,677,318
Veenstra  Date of Patent: Jun. 30, 1987
 PROGRAMMABLE LOGIC STORAGE
ELEMENT FOR PROGRAMMABLE LOGIC
 Inventor: Kerry S. Veenstra, Concord, Calif.
 Assignee: Altera Corporation, Santa Clara,
 Appl. No.: 722,684
 Filed: Apr. 12,1985
 Int. CI.* H03K 19/177
 U.S. CI 307/465; 307/445;
 Field of Search 307/440, 445, 465;
 References Cited
U.S. PATENT DOCUMENTS
4,034,356 7/1977 Howley et al 307/465
4,422,072 12/1983 Cavlan 307/465 X .
4,433,331 2/1984 Kollaritsch 364/716 X
4,525,641 6/1985 Cruz et al 307/465
Elliott et al., "Array Logic Processing"; IBM-TDB;
vol. 16, No. 2, pp. 586-587; 7/1973.
Eggebrecht et al., "Programmable Logic Array with
Provision for Interrupts"; IBM-TDB; vol. 20, No. 2, pp. 745-746; 7/1977.
Andres, "MOS Programmable Logic Arrays", A Texas Instruments Application Report; No. CA-158, 10/1970.
Primary Examiner—Stanley D. Miller
Assistant Examiner—D. R. Hudspeth
Attorney, Agent, or Firm—Claude A. S. Hamrick
A storage element for use in a logic array including a flip-flop device and a complex logic circuit interconnected in such a way that the output of the complex logic circuit is an input to the flip-flop. A Toggle FlipFlop Control (TFFC) signal, an invert control (INV) signal, and a clock (CLK) signal are also inputs to the complex logic circuit. The output of the flip-flop connects to an output pad, an internal direct feedback line which is one of the means by which the flip-flop is connected to the comples logic circuit, and an external feedback bus which leads back to an associated ANDOR array. The inptu to the complex logic circuit is generated by the standard AND-OR array which is programmable to some degree.
15 Claims, 18 Drawing Figures