(54) METHOD FOR CALIBRATING
SEMICONDUCTOR TEST INSTRUMENTS
(75) Inventor: Toru Ibane, Tokyo (JP)
(73) Assignee: Advantest Corporation, Tokyo (JP)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 11/352,096
(22) Filed: Feb. 11, 2006
(65) Prior Publication Data
US 2006/0123881 Al Jun. 15, 2006
Related U.S. Application Data
(62) Division of application No. 10/479,726, filed as application No. PCT/JP02/05604 on Jun. 6, 2002, now Pat. No. 7,043,959.
(30) Foreign Application Priority Data
Jun. 7, 2001 (JP) 2001-172210
Feb. 7, 2002 (JP) 2002-30576
Mar. 19, 2002 (JP) 2002-75316
(51) Int. CI.
G01R 35/00 (2006.01)
(52) U.S. CI 73/1.42
(58) Field of Classification Search 73/1.42;
324/766
See application file for complete search history. (56) References Cited
U.S. PATENT DOCUMENTS 4,929,888 A 5/1990 Yoshida
5,894,081 A 4/1999 Ashuri 73/1.42
6,327,678 Bl 12/2001 Nagal 714/700
6,417,682 Bl 7/2002 Suzuki et al 324/755
ADJUST PHASE OF ONE CLOCK
SIGNAL INCLUDED IN EACH
GROUP ON THE BASIS OF
ONE STROBE SIGNAL
ADJUST PHASE OF EACH
STROBE SIGNAL ON THE BASIS
OF ONE CLOCK SIGNAL
FOR EVERY GROUP
ADJUST PHASE OF EACH CLOCK SIGNAL ON THE BASIS OF OPTIONAL STROBE SIGNAL FOR EVERY GROUP
