[54] METHOD OF DEPOSITING POLYSILICON, METHOD OF FABRICATING A FIELD EFFECT TRANSISTOR, METHOD OF FORMING A CONTACT TO A SUBSTRATE, METHOD OF FORMING A CAPACITOR
[75] Inventors: Michael Nuttall, Meridian; Er-Xuan Ping; Yongjun Jeff Hu, both of Boise, all of Id.
[73] Assignee: Micron Technology, Inc., Boise, Id.
[ * ] Notice: This patent issued on a continued prosecution application filed under 37 CFR 1.53(d), and is subject to the twenty year patent term provisions of 35 U.S.C. 154(a)(2).
[21] Appl. No.: 09/023,239 [22] Filed: Feb. 13, 1998
[51] Int. CI.7 H01L 21/4763
[52] U.S. CI 438/674; 438/680; 438/684
[58] Field of Search 438/256, 489,
438/482, 664, 607, 666, 417, 430, 488, 564, 642, 674, 677, 641, 399, 300, 305; 156/603; 427/255.1; 117/86; 257/616, 377, 382, 754, 755
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OTHER PUBLICATIONS
Wolf, Stanley, Dec. 1986, "Silicon Procesessing for The VLSI ERA", pp. 183 & 191.
Violette, Katherine E., et al., "Low Temperature Selective
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Primary Examiner—Olik Chaudhuri
Assistant Examiner—-William David Coleman
Attorney, Agent, or Firm—Wells, St. John, Roberts, Gregory
& Matkin PS.
[57] ABSTRACT
In a method of depositing polysilicon comprises providing a substrate within a chemical vapor deposition reactor, with the substrate having an exposed substantially crystalline region and an exposed substantially amorphous region. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to selectively deposit polysilicon on the crystalline region and not the amorphous region. In another aspect a method of fabricating a field effect transistor on a substrate comprises forming a gate dielectric layer and a gate over semiconductive material. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the source/drain regions and not on amorphous material, and forming elevated source/drains on the doped source/drain regions. In another aspect, a method of forming a contact to a substrate is disclosed. A contact opening is etched through amorphous insulating material over a node location ultimately comprising an outwardly exposed substantially crystalline surface. Within a chemical vapor deposition reactor, a gaseous precursor comprising silicon is provided under conditions effective to selectively deposit polysilicon on the outwardly exposed crystalline node location surface and not on the insulating material.
33 Claims, 5 Drawing Sheets
