(73) Assignee: Texas Instruments Incorporated,
Dallas, TX (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 284 days.
(21) Appl. No.: 11/188,668
(22) Filed: Jul. 25, 2005
(65) Prior Publication Data
US 2006/0026354 Al Feb. 2, 2006
(51) Int. CI.
(52) U.S. CI 711/118; 711/100; 711/154;
(58) Field of Classification Search 711/100,
711/118, 154, 170 See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS
5,276,835 A * 1/1994 Mohan et al 711/144
A processor adapted to couple to external memory. The processor comprises a controller and data storage. The data storage is usable to store local variables and temporary data and is configurable to operate in either a cache policy mode in which a miss results in an access of the external memory or in a scratch pad policy mode in which a miss does not result in an access of the external memory. The data storage comprises first and second portions, and wherein only one of said portions is active at a time for storing said local variables. When the active portion does not have sufficient capacity for additional local variables, the other portion becomes the active portion for storing local variables. When one portion is the active portion, the other portion is used to store the temporary data and such other portion is sufficiently large to contain the temporary data.
16 Claims, 11 Drawing Sheets