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(12) United States Patent ao) Patent No.: us 6,689,671 Bi
Yu et al. (45) Date of Patent: Feb. 10,2004
(54) LOW TEMPERATURE SOLID-PHASE
EPITAXY FABRICATION PROCESS FOR
MOS DEVICES BUILT ON STRAINED
(75) Inventors: Bin Yu, Cupertino, CA (US); Derick J.
Wristers, Bee Caves, TX (US)
(73) Assignee: Advanced Micro Devices, Inc.,
Sunnyvale, CA (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 36 days.
(21) Appl. No.: 10/151,946
(22) Filed: May 22, 2002
(51) Int. CI.7 H01L 21/20; H01L 21/36
(52) U.S. CI 438/486
(58) Field of Search 438/486, 478-485,
438/487, 491, 507-509
(56) References Cited
U.S. PATENT DOCUMENTS
Yeo et al. "Nanoscale Ulta-thin-body silicon-on-insulator P-MOSFET with a SiGe/Si Heterostructure channel" IEEE Electron Device Letters vol. 21, No. 4, Apr. 2000.*
* cited by examiner
Primary Examiner—Craig Thompson
A method of manufacturing a semiconductor device, comprising steps of:
(a) providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface thereof and having a pre-selected amount of lattice strain;
(b) forming a device structure in the semiconductor substrate by a process comprising forming at least one amorphous region in at least one portion of the strained lattice semiconductor layer; and
(c) thermal annealing at a minimum temperature sufficient to effect epitaxial re-crystallization of the at least one amorphous region to re-form a strained lattice semiconductor layer having substantially the pre-selected amount of lattice strain, whereby strain relaxation of the strained lattice semiconductor arising from thermal annealing is substantially eliminated or minimized.
12 Claims, 2 Drawing Sheets
U.S. Patent Feb. 10,2004 Sheet 2 of 2 US 6,689,671 Bl
LOW TEMPERATURE SOLID-PHASE EPITAXY FABRICATION PROCESS FOR MOS DEVICES BUILT ON STRAINED SEMICONDUCTOR SUBSTRATE
FIELD OF THE INVENTION
The present invention relates generally to the manufacture of high speed MOS semiconductor devices fabricated on strained lattice semiconductor substrates, and devices obtained thereby. Specifically, the present invention relates to an improved method of performing thermal annealing of amorphized and dopant-implanted regions of strained lattice semiconductor layers for effecting epitaxial re-crystallization thereof and dopant activation, without incurring significant stress relaxation of the strained lattice.
BACKGROUND OF THE INVENTION
Recently, there has been much interest in various approaches with the aim or goal of developing new semiconductor materials which provide increased speeds of electron and hole flow therethrough, thereby permitting fabrication of semiconductor devices, such as integrated circuit (IC) devices with higher operating speeds, enhanced performance characteristics, and lower power consumption. One such material which shows promise in attaining the goal of higher device operating speeds is termed "strained silicon".
According to this approach, a very thin, tensilely strained, crystalline silicon (Si) layer is grown on a relaxed, graded composition Si—Ge buffer layer several microns thick, which Si—Ge buffer layer in turn is formed on a suitable crystalline substrate, e.g., a Si wafer or a silicon-on-insulator (SOI) wafer. Strained Si technology is based upon the tendency of the Si atoms, when deposited on the Si—Ge buffer layer, to align with the greater lattice constant (spacing) of the Si and Ge atoms therein (relative to pure Si). As a consequence of the Si atoms being deposited on a substrate (Si—Ge) comprised of atoms which are spaced further apart, they "stretch" to align with the underlying Si and Ge atoms, thereby "stretching" or tensilely straining the deposited Si layer. Electrons and holes in such strained Si layers have greater mobility than in conventional, relaxed Si layers with smaller inter-atom spacings, i.e., there is less resistance to electron and/or hole flow. For example, electron flow in strained Si may be up to about 70% faster compared to electron flow in conventional Si. Transistors and IC devices formed with such strained Si layers can exhibit operating speeds up to about 35% faster than those of equivalent devices formed with conventional Si, without necessity for reduction in transistor size.
However, an important concern in the manufacture of practical semiconductor devices utilizing strained semiconductor layers, e.g., strained Si layers, is the requirement for maintaining the tensilely strained condition of the strained semiconductor layer throughout device processing, without incurring significant strain relaxation disadvantageously leading to reduction in electron/hole mobility resulting in degradation in device performance characteristics. For example, many device fabrication steps, including for example, annealing for re-crystallization of amorphized regions and activation of implanted dopant species, frequently involve high temperature processing at temperatures on the order of about 900-1,100° C. for intervals sufficient to result in significant relaxation in the tensile strain of the Si layer, which in turn results in a lowering of the electron
and hole mobilities therein to values comparable to those of conventional Si layers, whereby the potential advantages attributable to enhanced electron/hole mobility in the strained Si layer are partially or wholly lost.
5 Accordingly, there exists a need for improved methodology for fabrication of semiconductor devices with strained semiconductor layers, notably strained Si layers, which substantially eliminates, or at least minimizes, deleterious stress relaxation during device processing at elevated
1° temperatures, e.g., as in thermal annealing processing for re-crystallization and dopant activation of amorphized, dopant-implanted source and drain regions forming part of MOS-type transistors and CMOS devices.
The present invention, wherein thermal annealing pro
15 cessing for re-crystallization and dopant activation of amorphized, dopant-implanted source and drain regions forming part of MOS-type transistors and CMOS devices is performed at a minimum temperature sufficient to cause epitaxial re-crystallization of amorphous, dopant-implanted
20 region in a strained lattice semiconductor layer to re-form an epitaxial, strained lattice semiconductor layer having substantially the original amount of lattice strain, effectively eliminates, or at least minimizes, disadvantageous strain relaxation of the strained lattice semiconductor arising from
the thermal annealing. As a consequence, the inventive methodology facilitates manufacture of high speed, high performance, reduced power consumption semiconductor devices utilizing strained semiconductor technology. Further the methodology afforded by the present invention enjoys 30 diverse utility in the manufacture of numerous and various semiconductor devices and/or components therefor which require use of strained semiconductor technology for enhancement of device speed and lower power consumption.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is an improved method for manufacturing a semiconductor device compris40 ing a strained lattice semiconductor layer.
Another advantage of the present invention is an improved method for manufacturing a semiconductor device comprising epitaxial re-crystallization of an amorphous, dopant-implanted region of a strained lattice semiconductor 45 layer without incurring significant stress relaxation.
Yet another advantage of the present invention is an improved method for manufacturing high-speed MOS-type semiconductor devices comprising strained lattice semiconductor layers.
Still another advantage of the present invention is improved, high-speed MOS-type semiconductor devices fabricated on or within substrates including strained lattice semiconductor layers. 55 Additional advantages and other aspects and features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present 60 invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the invention, the foregoing and other advantages are obtained in part by a method of manufac65 taring a semiconductor device, comprising the steps of:
(a) providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface