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US006278332B1
(12) United States Patent ao) Patent No.: us 6,278,332 Bi
Nelson et al. (45) Date of Patent: Aug. 21,2001
(54) CHARGE PUMP FOR LOW-VOLTAGE, LOWJITTER PHASE LOCKED LOOPS
(75) Inventors: Dale Harvey Nelson, Shillington;
Lizhong Sun, Emmaus, both of PA
(US)
(73) Assignee: Agere Systems Guardian Corp.,
Miami Lakes, FL (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 09/504,515
(22) Filed: Feb. 15, 2000
(51) Int. CI.7 H03L 7/085; H03L 7/089
(52) U.S. CI 331/17; 331/8; 331/25;
327/156; 327/157; 327/108; 327/111
(58) Field of Search 331/1 A, 8, 16,
331/17, 18, 25; 326/21, 26, 27; 327/156-159, 108-112; 375/376; 455/260
(56) References Cited
U.S. PATENT DOCUMENTS
5,532,636 * 7/1996 Mar et al 327/543
5,809,097 9/1998 Lakshmikumar .
5,886,551 3/1999 Narahara .
5,898,336 4/1999 Yamaguchi .
5,945,855 * 8/1999 Momtaz 327/157
5,986,485 11/1999 O'Sullivan .
5,987,085 11/1999 Anderson .
6,169,458 * 1/2001 Shenoy et al 331/17
OTHER PUBLICATIONS
B. Razavi (ED.), "Monolithic Phase-Locked Loops & Clock Recovery Circuits, Theory & Design," IEEE Press, 1997, pp. 25-28.
Floyde M. Gardner, "Charge-Pump Phase-Lock Loops," IEEE Trans. Comm., vol. COM-28, Nov. 1980, pp. 1849-1858.
Ian A. Young, et al., "A PLL Clock Generator with 5 to 110 Mhz of Lock Range Microprocessors," IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1599-1607.
* cited by examiner
Primary Examiner—David Mis
(74) Attorney, Agent, or Firm—Duane, Morris & Heckscher LLP
(57) ABSTRACT
An integrated circuit has a phase-locked loop (PLL) frequency synthesizer circuit which has a charge pump circuit for providing an output control voltage to adjust an oscillator frequency in response to fast and slow signals provided by a phase detector. The charge pump circuit has first and second current sources, and a switching network for selectively coupling, in response to said fast signal, the first current source to one of an internal node and an output node coupled to an output capacitor and having an output voltage, and, in response to said slow signal, the second current source to one of the internal node and the output node. The charge pump circuit has first and second unity gain buffers coupled in parallel at their inputs to the output node and at their outputs to the internal node, wherein the first buffer is configured to have a voltage tracking range approximately up to a positive supply rail and the second buffer is configured to have a voltage tracking range approximately down to a negative supply rail, wherein the voltage tracking ranges of said buffers overlap each other, to provide an overall substantially rail-to-rail voltage tracking range.
18 Claims, 3 Drawing Sheets
