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US007858465B2
(12) United States Patent ao) Patent No.: Us 7,858,465 B2
Komukai et al. (45) Date of Patent: Dec. 28,2010
(54) SEMICONDUCTOR DEVICE COMPRISING TRANSISTOR AND CAPACITOR AND METHOD OF MANUFACTURING THE SAME
(75) Inventors: Toshiaki Komukai, Kawasaki (JP);
Hideaki Harakawa, Kawasaki (JP)
(73) Assignee: Kabushiki Kaisha Toshiba, Tokyo (JP)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 153 days.
(21) Appl.No.: 12/031,297
(22) Filed: Feb. 14, 2008
(65) Prior Publication Data
US 2008/0197398 Al Aug. 21,2008
(30) Foreign Application Priority Data
Feb. 19,2007 (JP) 2007-38327
(51) Int. CI.
H01L 21/8238 (2006.01)
(52) U.S. CI 438/210; 438/171; 438/190;
438/238; 438/329; 438/381; 438/396; 438/397;
438/398; 438/399
(58) Field of Classification Search 257/7,
257/296, 306, E25.029, E21.576; 438/199, 438/239, 253, 256, 396-399, 171, 190, 210, 438/238, 329, 381 See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS
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6,146,931 A * 11/2000 Nunokawaetal 438/172
6,376,370 Bl * 4/2002 Farrar 438/678
6,569,717 Bl * 5/2003 Murade 438/149
6,664,580 B2 * 12/2003 Jao 257/296
6,872,966 B2 * 3/2005 Akiyamaetal 257/14
6,958,291 B2 * 10/2005 Yu et al 438/637
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7,420,227 B2* 9/2008 Chang etal 257/197
2005/0139887 Al * 6/2005 Song 257/296
2005/0205918 Al* 9/2005 Abiko 257/303
2006/0118823 Al * 6/2006 Parikh et al 257/194
FOREIGN PATENT DOCUMENTS
JP 2000-357773 12/2000
OTHER PUBLICATIONS
S. M. Sze. Semiconductor Devices. Physics and Technology, 2nd
Edition. (C) 2002 John Wiley and Sons, p. 398 *
M. Annaratone. Digital CMOS Circuit Design. (C) 1986, Kluwer
Academic Publishers, pp. 62-63.*
* cited by examiner
Primary Examiner—N Drew Richards
Assistant Examiner—Jae Lee
(74) Attorney, Agent, or Firm—Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
A semiconductor device according to an embodiment of the present invention includes: a transistor including, a gate insulator formed of an insulating layer deposited on a substrate, and a gate electrode formed of an electrode layer deposited on the insulating layer; a capacitor including, a first capacitor electrode formed of the electrode layer, a first capacitor insulator formed on the first capacitor electrode, a second capacitor electrode formed on the first capacitor insulator, a second capacitor insulator formed on the second capacitor electrode, and a third capacitor electrode formed on the second capacitor insulator; and line patterns which are in contact with a contact plug for the transistor, a contact plug for the first capacitor electrode, a contact plug for the second capacitor electrode, and the third capacitor electrode.
17 Claims, 12 Drawing Sheets