[54] DECODING CIRCUIT FOR USE IN
SEMICONDUCTOR READ ONLY MEMORY
[75] Inventor: Yukio Fuji, Kanagawa, Japan
[73] Assignee: NEC Corporation, Tokyo, Japan
[21] Appl. No.: 448,857
[22] Filed: May 24, 1995
[30] Foreign Application Priority Data
May 24, 1994 [JP] Japan 6-109858
[51] Int. CI.6 G11C 8/00
[52] U.S. CI 365/230.01; 365/230.06
[58] Field of Search 365/230.03, 230.06,
365/190, 230.01
[56] References Cited
U.S. PATENT DOCUMENTS
5,159,215 10/1992 Murotani 365/230.06
5,297,084 3/1994 Ban 365/230.06
5,440,518 8/1995 Hazani 365/230.03
FOREIGN PATENT DOCUMENTS
0277695 12/1987 Japan 365/230.06
4-95298 3/1992 Japan .
5-347094 12/1993 Japan .
Primary Examiner—David C. Nelms
Assistant Examiner—Trong Phan
Attorney, Agent, or Firm—Foley & Lardner
A decoding circuit for use in a semiconductor read only memory includes a predecoding unit receiving a first address signal group of a given address, for generating a plurality of word selection driving signals, and a plurality of decoder blocks each receiving a second address portion of the same address different from the first address signal group. Each of the decoder blocks includes a selecting unit receiving the second address signal group for outputting an active first word selection control signal when the decoder block is designated by the second address signal group, and a pair of word selecting units receiving the first word selection control signal and a third address signal group of the same address different from the first and second address signal groups, for generating a pair of second complementary word selection control signals and another pair of third complementary word selection control signals. Each decoder block also includes a plurality of decoding units each including a series-circuit constituted of first, second, third and fourth series-connected transistors, having their control electrode connected to receive the second and third complementary word selection control signals, respectively. Opposite ends of the series-circuit are connected to receive a corresponding one of the word selection driving signals. A connection node between the first and second transistors generates a first word selecting signal, and a connection node between the third and fourth transistors generates a second word selecting signal. Only one of the word selecting signal is activated at a time.
