Illlllllllllllllllllllllllllllllllllllllllllllllll
US006725415B2
(12) United States Patent ao) Patent No.: us 6,725,415 B2
Ishiwaki (45) Date of Patent: Apr. 20,2004
(54) ARITHMETIC UNIT PERFORMING CYCLIC REDUNDANCY CHECK AT HIGH SPEED
(75) Inventor: Masahiko Ishiwaki, Hyogo (JP)
(73) Assignee: Mitsubishi Denki Kabushiki Kaisha, Tokyo (JP)
( * ) Notice: Subject to any disclaimer, the term ol this patent is extended or adjusted under 35 U.S.C. 154(b) by 468 days.
(21) Appl. No.: 09/769,413
(22) Filed: Jan. 26, 2001
(65) Prior Publication Data
US 2001/0020288 Al Sep. 6, 2001 (30) Foreign Application Priority Data
Mar. 6, 2000 (JP) 2000-060330
(51) Int. CI.7 H03M 13/09; G06F 7/52;
G06F 7/72
(52) U.S. CI 714/781; 708/492
(58) Field of Search 714/781-785;
708/492
(56) References Cited
U.S. PATENT DOCUMENTS
A hold circuit holds results of processing in an arithmetic circuit collectively receiving four bits from inputs. The inventive arithmetic unit collectively processes an input data string, which has generally been processed bit by bit, by four bits at a time, whereby a CRC arithmetic operation can be speeded up. More preferably, the arithmetic unit can flexibly deal with change of a generating polynominal set in the arithmetic circuit when rendering set data corresponding to the generating polynomial changeable.
9 Claims, 19 Drawing Sheets
