4,663,708 5/1987 Taub 395/325
4,733,353 3/1988 Jaswa 395/650
4,775,934 10/1988 Houri et al 395/375
4,833,638 5/1989 Vollaro 395/650
5,056,000 10/1991 Chang 395/325
5222.237 6/1993 Hillis 395/650
5,388,262 2/1995 Hillis 395/650
Requa et al, 'The Plecewise Data Flow Architecture:Architecural Concepts." IEEE Transactions on Computers, vol. C-32, No. 5, May 1983.
P.Tang et al., "Processor Self-^Scheduling for Multiple-Nested Parallel Loops" Proc. Int'l Conf. on Parallel Processing, Aug. 1986, pp. 528-535.
R.Gupta, 'The Fuzzy Barrier: A Mechanism for High Speed Synchronization of Processors," Proc. Third Int'l Conf. on Architectural Support for Programming Languages and Operating Systems, Apr. 1989, pp. 54-63.
Primary Examiner—Paul V. Kulik
A method and apparatus are disclosed for aligning a plurality of multi-processors. The apparatus preferably comprises an alignment unit associated with each processor and a logic network for combining the output of the alignment unit and for broadcasting information to these units. Alignment is achieved by inserting in the instruction stream from each processor that is to be aligned a request for alignment, by testing for prior completion of any instructions that must be completed and by causing all processors to wait until they have all made the request for alignment and completed necessary prior instructions. The alignment unit associated with each processor monitors the instruction stream to detect a request for alignment. The logic network illustratively is an array of AND gates that tests each alignment unit to determine if it has detected a request for alignment. When all the units have made such a request, the logic network informs the alignment units; and the alignment units inform the processors.
1 Claim, 4 Drawing Sheets