United States Patent  [ii] Patent Number: 4,680,609
Calder et al.  Date of Patent: Jul. 14,1987
 STRUCTURE AND FABRICATION OF
VERTICALLY INTEGRATED CMOS LOGIC
 Inventors: Iain D. Calder, Nepean; Thomas W.
Macelwee; Abdalla A. Naem, both of
Ottawa, all of Canada
 Assignee: Northern Telecom Limited, Montreal, Canada
 Appl. No.: 653,192
 Filed: Sep. 24, 1984
 Int. CI.4 H01L 27/02; H01L 29/04;
 U.S. CI 357/42; 357/59;
357/23.7; 357/23.14; 357/23.11
 Field of Search 357/42, 23.7, 28.14,
357/59 E, 23.11
 References Cited
U.S. PATENT DOCUMENTS
3,967,988 7/1976 Davidsohn 357/23.11'
4,555,721 11/1985 Bansal et al 357/59 E
OTHER PUBLICATIONS Faggin et al., "Silicon Gate Technology", Solid State
A vertically integrated CMOS logic gate has spaced semiconductor layers with control gates located between the layers and insulated from them by gate oxide. Transistors formed in one semiconductor layer are vertically aligned with transistors formed in the other semiconductor layer. Pairs of vertically coincident transis^ tors have common control gates and certain of the pairs have integral drain regions. Transistors in one layer are series connected in an open loop configuration and transistors in the other layer are parallel connected in a closed loop configuration. The logic gate function depends on voltages applied to the common control gates and to the open and closed loops. By the vertical integration, a two-input NAND or NOR gate can be made using less area than that required for two simple MOS transistors.
19 Claims, 29 Drawing Figures