Input circuit and output circuit

(54) INPUT CIRCUIT AND OUTPUT CIRCUIT

(75) Inventors: Hiroyuki Takahashi; Yuuji Matsui,

both of Tokyo (JP)

(73) Assignee: NEC Corporation (JP)

( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.

(21) Appl. No.: 09/886,715

(22) Filed: Jun. 21, 2001

(30) Foreign Application Priority Data

Jun. 23, 2000 (JP) 2000-190112

(51) Int. C I. G11C 7 00

(52) U.S. CI 327/546; 327/427

(58) Field of Search 327/355, 361,

327/427, 434, 437, 538, 543, 545, 546, 574, 581, 595; 323/282, 288, 289

(56) References Cited

U.S. PATENT DOCUMENTS

5,654,571 A * 8/1997 Tsuji 257/357

6,005,436 A * 12/1999 Shibayama et al 327/546

The output circuit of the present invention which produces an external signal at a first voltage from an internal signal at a reduced second voltage and which outputs the external signal from an output terminal, comprises: first and second MOS transistors having drains connected to the output terminal, and having gates connected to a control signal line; a third MOS transistor having a source connected to a power source of the first voltage, and having a drain connected to a source of the first MOS transistor; a fourth MOS transistor having a source connected to a ground, having a drain connected to a source of the second MOS transistor, and having a gate connected to an internal signal line; a voltage changer, which changes the voltage of the internal signal, connected to the gate of the third MOS transistor; a first capacitor connected between a gate of the first MOS transistor and a gate of the third MOS transistor; and a second capacitor connected between a gate of the second MOS transistor and a gate of the fourth MOS transistor.

13 Claims, 8 Drawing Sheets