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US006812727B2
(12) United States Patent ao) Patent No.: us 6,812,727 B2
Kobayashi (45) Date of Patent: Nov. 2,2004
(54) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND TESTING METHOD THEREOF
(75) Inventor: Norifumi Kobayashi, Kanagawa (JP)
(73) Assignee: Kabushiki Kaisha Toshiba, Tokyo (JP)
( * ) Notice: Subject to any disclaimer, the term ol this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 10/384,621
(22) Filed: Mar. 11, 2003
(65) Prior Publication Data
US 2003/0184336 Al Oct. 2, 2003 (30) Foreign Application Priority Data
Mar. 11, 2002 (JP) 2002-065025
(51) Int. CI.7 G01R 31/26
(52) U.S. CI 324/765; 324/763
(58) Field of Search 324/763-765,
324/158.1; 714/700, 733; 368/113-118;
327/152, 269
(56) References Cited
U.S. PATENT DOCUMENTS
6,057,691 A * 5/2000 Kobayashi 324/617
A semiconductor integrated circuit device comprises: a semiconductor substrate on which a semiconductor chip is provided; a plurality ol phase comparators, provided on said semiconductor substrate, with input signals to said semiconductor integrated circuit Irom outside serving as one inputs thereol; and a variable delay circuit, provided on said semiconductor substrate, configured to adjust a timing ol a relerence clock signal which is used lor a phase comparison; wherein distributed relerence clock signal signals into which the relerence clock signal is distributed so as to reach at the same time said plurality ol phase comparators, are set as the other inputs ol said phase comparators.
9 Claims, 7 Drawing Sheets
