Non-diffusion junction split-gate nonvolatile memory cells and arrays ...

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US007723774B2

(12) United States Patent

Chen et al.

(io) Patent No.: (45) Date of Patent:

US 7,723,774 B2 May 25, 2010

(54) NON-DIFFUSION JUNCTION SPLIT-GATE
NONVOLATILE MEMORY CELLS AND
ARRAYS, METHODS OF PROGRAMMING,
ERASING, AND READING THEREOF, AND
METHODS OF MANUFACTURE

(75) Inventors: Changyuan Chen, Sunnyvale, CA (US);

Ya-Fen Lin, Saratoga, CA (US); Dana
Lee, Saratoga, CA (US)

(73) Assignee: Silicon Storage Technology, Inc.,

Sunnyvale, CA (US)

( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 238 days.

(21) Appl.No.: 11/775,851

(22) Filed: Jul. 10, 2007

(65) Prior Publication Data

US 2009/0016113 Al Jan. 15, 2009

(51) Int. CI.

H01L 29/788 (2006.01)

(52) U.S. CI 257/315; 257/316; 257/319;

257/E21.68

(58) Field of Classification Search 257/315,

257/316,319; 365/185 See application file for complete search history.

6,825,084 B2 11/2004 Oguraetal. 2005/0243603 Al * 11/2005 Kobayashi et al 365/185.17

OTHER PUBLICATIONS

Y. Sasago et al, "90-nm-node Multi-level AG-AND Type Flash
Memory With Cell Size of True 2-F/sup 2/bit and Programming
Throughput of lOMB/s," published in the 2003 IEDM Technical
Digest, pp. 34.2.1-34.2.4 (also pp. 823-826), Dec. 2003.
H. Kurata et al, "Self-boosted Charge Injection for 90-nmNode 4-GB
Multilevel AG-AND Flash Memories Programmable at 16 MB/s,"
published in the 2004 Digest of Technical Papers—Symposium on
VLSI circuits, pp. 72-73, Jun. 2004.

* cited by examiner

Primary Examiner—Jerome Jackson, Jr.

Assistant Examiner—Dale Page

(74) Attorney, Agent, or Firm—DLA Piper LLP (US)

Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.

46 Claims, 19 Drawing Sheets