Trench capacitor DRAM cell with diffused bit lines adjacent to a trench

United States Patent m

Riemenschneider et al.

[11]

[45]

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US005105245A

Patent Number:
Date of Patent:

5,105,245 Apr. 14,1992

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FOREIGN PATENT DOCUMENTS

66081 12/1982 European Pat. Off. .
88451 3/1983 European Pat. Off. .

(List continued on next page.)
Primary Examiner—Rolf Hille
Assistant Examiner— Robert P. Limanek
Attorney, Agent, or Firm—Richard A. Stoltz; Rene E.
Grossman; Richard L. Donaldson

OTHER PUBLICATIONS

IBM Technical Disclosure Bulletin, vol. 31, No. 7, "High Density Memory Cell Structure with Two Access Transistors".

[57] ABSTRACT

A plurality of trenches (26, 28) of a DRAM cell array formed in a (P—) epitaxial layer (11) and a silicon substrate (12), and storage layers (38,40) are grown on the sidewalk (34, 36) and bottom (not shown) of the trenches (26, 28). Highly doped polysilicon capacitor electrodes (42, 44) are formed in the trenches (26, 28). Sidewall oxide filaments (50,54) and in situ doped sidewall conductive filaments (66,68) are formed and thermal cycles are used to diffuse dopant from sidewall conductive filaments (66, 68) into upper sidewall portions (62,64) to form diffused source regions (70,72) of pass gate transistors (90) for each cell.

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Page 2

Jambotkar; IBM TDB, vol. 27, No. 2, Jul. 1984; pp. 1313-1320 shows a memory cell formed in a trench. Clarke et al.; IBM TDB, vol. 17, No. 9; Feb. 1975; pp. 2579-2850 shows embodiments of two adjacent dRAM cells. One embodiment uses a mesa transistor structure and the other uses a V-groove cut between the cells. Chang et al.; IBM TDB; vol. 22, No. 8B, Jan. 1980; pp. 3683-3687 shows a vertical dRAM cell using either a V-groove or a U-groove.

Kenney; IBM TDB; vol. 23, No. 9; Feb. 1981; pp.

4052-4053 shows a V-groove dRAM cell.

Fatula et al.; IBM TDB, vol. 22, No. 8A; Jan. 1980; pp.

3204-3205 shows a U-groove memory cell.

Chang et al.; IBM TDB; vol. 22, No. 7; Dec. 1979; pp.

2768-2771 shows the use of filament remnants on the

side of trenches as word lines.

Barson; IBM TDB; vol. 23, No. 7; Dec. 1978; pp. 2755-2756 shows a U-groove dRAM cell similar to that of Fatula et al.

Kenney; IBM TDB, vol. 23, No. 3; Aug. 1980; pp. 967-969 shows a double polysilicon Hi-C type dRAM cell formed so that portions of the cell are formed in a V-groove.

Lee et al.; IBM TDB; vol. 22, No. 8B; Jan. 1980; pp. 3630-3634 shows embodiments of V-groove dRAM cell.

Nakajima et al.; IEDM; 1984; pp. 240-243 shows a dRAM cell formed on a mesa of a substrate. The capacitor is formed surrounding the mesa.

11 Claims, 2 Drawing Sheets