Polishing method for thin gates dielectric in semiconductor process

United States Patent [w]

Gilmer et al.

US005985706A [ii] Patent Number: 5,985,706 [45] Date of Patent: Nov. 16,1999

[54] POLISHING METHOD FOR THIN GATES DIELECTRIC IN SEMICONDUCTOR PROCESS

[75] Inventors: Mark C. Gilmer, Austin; Mark I.

Gardner, Cedar Creek, both of Tex.

[73] Assignee: Advanced Micro Devices, Inc.,

Sunnyvale, Calif.

[21] Appl. No.: 08/853,499 [22] Filed: May 8, 1997

Int. CI. II01I. 21/8238

438/199; 438/588; 438/692;

438/225

Field of Search 438/759, 588,

438/225, 692, 691, 693, 199, 585, 201, 207, 218, 233, 277, 223, 227; 134/29

[51]

[52] U.S. CL [58]

[56]

References Cited U.S. PATENT DOCUMENTS

5,663,086 9/1997 Rostoker et al 438/210

5,866,458 2/1999 Lee 438/277

Primary Examiner—Charles Bowers

Assistant Examiner—Hsien-Ming Lee

Attorney, Agent, or Firm—Kevin L. Daffer; Conley, Rose &

Tayon

A semiconductor process in which an initial gate dielectric layer is formed on an upper surface of a semiconductor substrate. The initial gate dielectric layer is polished with a chemical mechanical polish to produce a finished gate dielectric layer. A thickness of the finished gate dielectric layer is less than a thickness of the initial gate dielectric layer and the thickness of the preferred finished gate dielectric layer is in the range of approximately 25 to 60 angstroms. In one embodiment, the initial gate dielectric layer is formed by thermally oxidizing the semiconductor substrate in an oxygen bearing ambient maintained at a temperature in the range of approximately 600° C. to 900° C. In an alternative embodiment, the formation of the initial gate dielectric layer is achieved by depositing an oxide. In this embodiment, the deposited oxide is preferably fabricated by a chemical vapor deposition process using a TEOS source in a CVD reactor chamber maintained at a temperature in the range of approximately 300° C. to 600° C. and a pressure of less than approximately two torrs. In a presently preferred embodiment, the polishing includes depositing a slurry on a ceramic polishing pad and applying the gate dielectric to the polishing plate in the presence of the slurry while rotating the ceramic plate with respect to the semiconductor substrate. The slurry preferably comprises fumed silica suspended in a suspending solution. The suspending solution preferably comprises KOH or NH3OH. In one embodiment, the polishing plate is comprised of aluminum oxide.

19 Claims, 2 Drawing Sheets

1

POLISHING METHOD FOR THIN GATES
DIELECTRIC IN SEMICONDUCTOR
PROCESS

BACKGROUND OF THE INVENTION 5

1. Field of the Invention

The present invention relates to the field of semiconductor processing and more particularly to a method of fabricating ultra thin gate dielectrics using a chemical mechanical 10 polishing technique.

2. Description of the Relevant Art

The fabrication of MOS (metal-oxide-semiconductor) transistors within a semiconductor substrate is well known. Typically, the substrate is divided into a plurality of active :5 and isolation regions through an isolation process such as field oxidation or shallow trench isolation. A thin oxide is then grown on an upper surface of the semiconductor substrate in the active regions. This thin oxide serves as the gate oxide for subsequently formed transistors. Next, a 20 plurality of polysilicon gate structures are formed wherein each polysilicon gate traverses an active region effectively dividing the active region into two regions referred to as the source region and the drain region. After formation of the polysilicon gates, an implant is performed to introduce an 25 impurity distribution into the source/drain regions.

As transistor channels shrink below 0.5 micron, the limitations of conventional transistor processing become more apparent. To combat short channel effects in these smaller transistors, the depth of the source/drain junctions 30 and the thickness of the gate oxides must be reduced. Thin oxides present significant manufacturing challenges to the manufacturer. The uniformity of the gate dielectric film across the wafer becomes more critical as the film thickness

35

decreases. A 5 angstrom variation in film thickness across a wafer is far more significant in a 50 angstrom film than a 150 angstrom film. Greater control over oxide growth rates, uniformity, and etch rates is needed to insure that the thinner dielectric can be consistently reproduced in a manufacturing environment. Conventional gate formation techniques, 40 which typically consist of immersing a plurality of wafers into an oxidation tube maintained at a temperature sufficient to thermally oxidize exposed silicon, do not provide sufficient film thickness control for the reliable fabrication of ultra-thin films (i.e., films with a thickness less than approxi- 45 mately 65 angstroms).

Despite the manufacturing difficulties noted, thin gate dielectrics are desirable not only to minimize short channel effects, but also because the transistor drive current is 5Q roughly inversely proportional to the gate oxide thickness over a wide range of operating conditions. Because higher drive currents result in faster devices, a great deal of effort has been directed towards reducing the gate oxide thickness (as well as other transistor geometries including channel 5J length and junction depth) without significantly reducing the reliability of the integrated circuit. Therefore, it would be highly desirable to fabricate ultra-thin MOS gate dielectrics with a consistently reproducible and manufacturable process. 6Q

SUMMARY OF THE INVENTION

The problems identified above are in large part addressed by a semiconductor process in which an initial gate dielectric layer is formed on an upper surface of a semiconductor 65 substrate. The initial gate dielectric layer is polished with a chemical mechanical polish to produce a finished gate

2

dielectric layer. A thickness of the finished gate dielectric layer is less than a thickness of the initial gate dielectric layer and the thickness of the finished gate dielectric layer is in the range of approximately 25 to 60 angstroms. Preferably the semiconductor substrate comprises a monocrystalline silicon substrate and still more preferably includes a p-type epitaxial layer formed on a p+ silicon bulk. A preferred resistivity of the p-type epitaxial layer is in the range of approximately 10 to 15 Q-cm. A peak impurity concentration of the p+ silicon bulk is typically greater than approximately 1019 atoms/cm3. In one embodiment, the initial gate dielectric layer is formed by thermally oxidizing the semiconductor substrate in an oxygen bearing ambient maintained at a temperature in the rang of approximately 600° C. to 900° C. In an alternative embodiment, the formation of the initial gate dielectric layer is achieved by depositing an oxide. In this embodiment, the deposited oxide is preferably fabricated by a chemical vapor deposition process using a TEOS source in a CVD reactor chamber maintained at a temperature in the range of approximately 300° C. to 600° C. and a pressure of less than approximately two torrs.

In a presently preferred embodiment, the polishing includes depositing a slurry on a ceramic polishing plate and applying the gate dielectric to the polishing plate in the presence of the slurry while rotating the ceramic plate with respect to the semiconductor substrate. The slurry preferably comprises fumed silica suspended in a suspending solution. The suspending solution preferably comprises KOH or NH3OH. In one embodiment, the polishing plate is comprised of aluminum oxide.

The present invention further contemplates a process for fabricating a dual gate dielectric thickness integrated circuit. The process includes forming a gate dielectric layer having an initial thickness on an upper surface of a semiconductor substrate. The thickness of a first portion of the gate dielectric layer is then increased to a first thickness. The first portion of the gate dielectric layer is aligned over a first region of the semiconductor substrate. Thereafter, the gate dielectric layer is polished with a chemical mechanical polish to reduce the thickness of the first portion of the gate dielectric layer to a final thickness that is less than the first thickness and greater than the initial thickness such that the gate dielectric layer includes a first portion which has a final thickness and a second portion which has an initial thickness. The second portion of the gate dielectric layer is aligned over a second region of the semiconductor substrate. The second region is laterally displaced from the semiconductor substrate first region. First and second conductive gate structures are then formed over the first and second portions respectively of the gate dielectric layer. The conductive gate structures are further aligned over respective channel regions within the first and second regions of the semiconductor substrate. A first and a second pair of source/ drain structures are then formed within first and second pairs of source/drain regions of the semiconductor substrate. The pairs of source/drain regions are laterally displaced on either side of respective channel regions of the semiconductor substrate.

The preferred semiconductor substrate includes a p-type epitaxial layer formed on an upper surface of a p+ silicon bulk. A resistivity of the p-type epitaxial layer is preferably in the range of approximately 10 to 15 Q-cm. The preferred formation of the gate dielectric layer is accomplished by immersing the semiconductor substrate in an oxygen bearing ambient maintained at a temperature in the range of approximately 700° C. to 900° C. to thermally oxidize an upper surface of the semiconductor substrate. The preferred