United States Patent m
Miyamoto
[li] 4,424,578 [45] Jan. 3,1984
[54] BIPOLAR PROM
[75] Inventor: Junichi Miyamoto, Yokohama, Japan
[73] Assignee: Tokyo Shibaura Denki Kabushiki Daisha, Japan
[21] Appl. No.: 283,011
[22] Filed: Jul. 13,1981
[30] Foreign Application Priority Data
Jul. 14, 1980 [JP] Japan 55-95844
[51] Int. CI.3 G11C 11/40; Gl 1C 17/00
[52] U.S. CI 365/104; 357/51;
357/59
[58] Field of Search 365/104; 357/67 S, 2,
357/51, 59, 71
[56] References Cited
U.S. PATENT DOCUMENTS
3,570,114 3/1971 Tsaug 29/577
3,717,852 2/1973 Abbas et al 357/71
3,980,505 9/1976 Buckley 357/2
4,146,902 3/1979 Tanimoto et al. 357/6
FOREIGN PATENT DOCUMENTS
54-1430 1/1979 Japan 357/67 S
2103900 9/1971 Fed. Rep. of Germany
2300847 1/1975 Fed. Rep. of Germany
OTHER PUBLICATIONS
"Study on Cell Structure of P-ROM Using Polysilicon Resistor," Proceedings of 1979 Meeting, Semiconductor Material Department of the Japan Electronic Communication Institute, p. 130.
Primary Examiner—George G. Stellar
Attorney, Agent, or Firm—Firinegan, Henderson,
Farabow, Garrett and Dunner
[57] ABSTRACT
A semiconductor memory device has memory cells, each including an emitter region formed in a base region as a bit line, a barrier layer formed in a hole formed in the oxide layer to be in contact the emitter region, a high resistance layer formed thereon, and a metal wiring layer as a word line in contact with the high resistance layer. By applying a voltage between the bit line and the word line, the metal wiring layer melts the part where both these lines cross, punches through the high resistance layer, and reaches the barrier layer, thus short-circuiting both these lines and accomplishing writing.
11 Claims, 10 Drawing Figures
