Ceramic multilayer circuit board and semiconductor module

[54] CERAMIC MULTILAYER CIRCUIT BOARD AND SEMICONDUCTOR MODULE

[75] Inventors: Nobuyuki Ushifusa; Hiroichi

Shinohara, both of Hitachi; Kousei
Nagayama, Ibaraki; Satoru Ogihara;
Tasao Soga, both of Hitachi, all of
Japan

[73] Assignee: Hitachi, Ltd., Tokyo, Japan

[21] Appl. No.: 58,255

[22] Filed: Jun. 4, 1987

[30] Foreign Application Priority Data

Jun. 6, 1986 [JP] Japan 61-130136

[51] Int. C1.+ H05K 01/03

[52] U.S. CI 361/395; 174/68.5;

361/414

[58] Field of Search 174/68.5; 361/414, 411,

361/395; 501/55, 80

[56] References Cited

U.S. PATENT DOCUMENTS

3,030,215 4/1962 Veatch et al 501/55 X

4,374,391 2/1983 Camliel 501/54 X

4,547,625 10/1985 Tosaki et al 501/54 X

4,620,264 10/1986 Ushifusa et al 174/68.5 X

4,672,152 6/1987 Shinohara et al 361/414 X

4,685,033 8/1987 Inoue 174/68.5 X

FOREIGN PATENT DOCUMENTS

61-83674 4/1986 Japan 501/80

2162167 1/1986 United Kingdom 501/255

OTHER PUBLICATIONS

Anderson et al., Low-Dielectric Glass Substrate, IBM Tech. Disc. Bull., vol. #14, #9, Feb. 1972, p. 2581.

Primary Examiner—R. R. Kucia

Attorney, Agent, or Firm—Antonelli, Terry & Wands

[57] ABSTRACT

A ceramic multilayer circuit board comprising ceramic layers and wiring conductor layers laminated alternately, in which the ceramic layer has a thermal expansion coefficient lower than that of the wiring conductor and not lower than one half of that of the conductor layer and is formed from a glass which softens at a temperature not higher than the melting point of the wiring conductor layer; a semiconductor module having a high reliability in its solder joint part comprising said ceramic multilayer circuit board mounted with a ceramic carrier substrate being mounted with a semiconductor device, said board being able to use a silver or copper conductor having a good electro-conductivity; and an amorphous glass powder for said ceramic multilayer circuit board.

9 Claims, 2 Drawing Sheets

4,8:

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CERAMIC MULTILAYER CIRCUIT BOARD AND SEMICONDUCTOR MODULE

TECHNICAL FIELD

This invention relates to a novel ceramic multilayer circuit substrate, and particularly to a semiconductor module comprising a ceramic multilayer circuit board mounted with a carrier substrate, said substrate being mounted with a semiconductor device. Particularly, it relates to a semiconductor module structure in which a silver or copper conductor having a good electroconductivity can be used in the multilayer circuit board, and further the solder joint part of the semiconductor device has a good reliability.

BACKGROUND ART

To attain a higher operation speed in a large electronic computer, it is necessary to attain a higher signal propagation speed in a semiconductor device itself and in a system in which the device is packaged. In recent years, for semiconductor devices, the development of high-integration technology has resulted in markedly higher speed and higher integration, and the packaging technology has come to affect greatly on increasing the operation speed. As to the packaging technology, ceramic multilayer circuit substrates have come to be used in order to enable a high density packaging of semiconductor devices and to reduce the delay of electric signals. Previously, alumina has been generally used as the insulating material for ceramic multilayer circuit substrates. In recent years, however, to enhance the properties of the substrate further, there have been studied and developed low-temperature sintered substrate materials, such as those described in "multilayer ceramic substrate" [Japanese Patent Application Kokoku (PostExam. Publn.) No. 22,399/84], and low-temperature sintered material of low dielectric constant formed by bonding silica with glass, such as those described in "ceramic multilayer wiring circuit board" [Japanese Patent Application Kokai (Laid-open) No. 11,700/84]. In these circuit board materials, which are obtained by sintering the original material densely so as to contain as few pores as possible therein, the specific dielectric constant, which affects greatly on attaining a higher operation speed, is about 4 to 5 at the lowest.

Further, there have been already obtained, for the purpose of heat insulation, weight reduction, or sound insulation, substrates which contain pores within the ceramics, such as those described in "composite ceramic electronic material" [Japanese Patent Application Kokai (Laid-open) No. 89,212/82] and "process for producing foamed ceramic board" [Japanese Patent Application Kokai (Laid-open) No. 83,985/84]. However, no consideration has been given to these substrates for using them as the substrate material for large electronic computers in which a higher signal propagation speed is required.

On the other hand, with the advent of semiconductors of higher speed and higher density, methods have come to be used in which semiconductor devices are directly packaged on a ceramic multilayer circuit substrate in order to facilitate heat radiation and to increase the speed of the device. However, this packaging method has a problem in that as the size of the semiconductor device increases, the stress which develops between the semiconductor device material and the ceramic multilayer wiring circuit substrate material owing

to the temperature change during packaging increases. Accordingly, attempts have been made to bring the thermal expansion coefficient of the ceramic multilayer wiring circuit substrate close to that of the semiconduc

5 tor device. However, to obtain a high density wiring by using gold, copper, silver etc., which have a low electric resistance, as the wiring conductor material, the thermal expansion coefficient of the ceramic insulating material should be brought close to that of these con

10 ductor materials. Thus, the thermal expansion coefficient of the ceramic insulating material is required to be close to that of the semiconductor device material and that of the conductor material. However, no due consideration has been given to a packaging technology

15 suitable under these mutually contradictory conditions. In a ceramic multilayer circuit substrate, the insulating material is required to have as low a dielectric constant as possible to attain a higher signal propagation speed. Further, the conductor material used is required

20 to have a low electric resistance. As described, for example, in "ceramic multilayer wiring circuit board" [Japanese Patent Application Kokai (Laid-open) No. 11,700/84], a substrate material having a specific dielec

25 trie constant of 4 to 5 has been obtained which comprises silica, which has a low dielectric constant, bonded with glass. Further, since the material can be fired at a temperature not higher than 1,000° C, conductor materials of low electric resistance, namely gold,

3q copper, silver etc., can be used in combination therewith. Further, the thermal expansion coefficient of the ceramic multilayer circuit board material has been brought as close to that of the semiconductor device as possible, and is much different from that of the conduc

35 tor material. Thus, no due attention has been paid to attaining a high density wiring of the internal circuit and yet mounting the semiconductor devices in a high density and with good reliability. The object of this invention is to provide a packaging

40 technology which gives a ceramic multilayer circuit substrate comprising a ceramic insulating material of lower specific dielectric constant and such conductor material of low resistance as gold, copper, or silver wired in a high density thereon and which makes it

45 possible to mount the semiconductor devices in a high density and with good reliability.

DISCLOSURE OF INVENTION

According to this invention, there is provided a ce50 ramie multilayer circuit board comprising ceramic layers and wiring conductor layers laminated alternately, in which the ceramic layer has a thermal expansion coefficient lower than that of the wiring conductor and not lower than one half of that of the conductor layer 55 and is formed from a glass which softens at a temperature not higher than the melting point of the wiring conductor layer.

BRIEF DESCRIPTION OF DRAWINGS

60 FIGS. 1 and 2 are each a longitudinal sectional view of a semiconductor module showing an embodiment of this invention.

BEST MODE FOR CARRYING OUT THE
INVENTION

In FIGS. 1 and 2, reference numbers 1 and 10 denote a semiconductor device, reference numbers 2 and 11 denote a material comprising, as the main component,