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United States Patent  [li] Patent Number: 4,717,912
Harvey et al.  Date of Patent: Jan. 5,1988
 APPARATUS FOR PRODUCING ANY ONE OF A PLURALITY OF SIGNALS AT A SINGLE OUTPUT
 Inventors: Paul W. Harvey, Santa Clara;
Bradford S. Kitson, Castro Valley; Warren K. Miller, Jr., Hayward, all of Calif.
 Assignee: Advanced Micro Devices, Inc., Sunnyvale, Calif.
 Appl. No.: 433,253
 Filed: Oct. 7,1982
 Int.Cl." H04Q1/00
 U.S. a 340/825.83; 307/465;
 Field of Search 340/825.83, 825.87,
340/825.89, 825.22; 307/57, 58, 80, 465, 468, 303, 62, 463, 269; 328/36, 57, 61, 104, 152, 62
 References Cited
U.S. PATENT DOCUMENTS
Re. 29,917 2/1979 Kumakawa et al 307/465
2,504,999 4/1950 McWhirter et al 328/104 X
2,863,049 12/1958 Lee et al 328/104
3,656,115 4/1972 Foerster 340/825.84
4,032,894 6/1977 Williams 340/825.87 X
4,044,312 8/1977 D'Ortenzio 307/464 X
4,124,899 11/1978 Birkner et al 307/465
4,157,480 6/1979 Edwards 307/465
4,422,072 12/1983 Cavlan 340/825.83 X
4,450,365 5/1984 Hoff, Jr. et al 328/61 X
Primary Examiner—Ulysses Weldon
Attorney, Agent, or Firm—Patrick T. King; Martin C.
An integrated circuit package having a plurality of pins and a plurality of output structures connected, respectively, to the plurality of pins. Each output structure selectively provides any one of four signals including a registered signal, non-inverted or inverted, or a nonregistered signal, non-inverted or inverted, to a pin. Each output structure is configurable or field-programmable by a user or purchaser of the package to provide it with any desired combination of registered and non-registered outputs.
35 Claims, 6 Drawing Figures
U.S. Patent Jan. 5,1988 Sheet 1 of 2 4,717,912
APPARATUS FOR PRODUCING ANY ONE OF A PLURALITY OF SIGNALS AT A SINGLE OUTPUT
TECHNICAL FIELD 5
The present invention relates generally to apparatus for producing any one of a plurality of signals at a single output and, more particularly, to output structure of a chip for connection to a pin of an integrated circuit package. 10
Logic functions are implemented using integrated circuit (IC) technology such as large scale integration (LSI). An integrated circuit package includes a chip, on ^ which the logic functions are implemented, a plurality of pins and an architecture known as output structures, among other integrated logic components on the chip. The output structures are coupled to the pins to transfer logic signals from the chip via the pins to other IC 20 packages.
A class of chips has been developed which are known as field-programmable logic families. The logic families are "field-programmable", which means that these chips can be programmed or modified by the chip users 25 or purchasers with the aid of readily available programming equipment to change the logic, as desired. For example, one member of this logic class is the field-programmable logic sequencer whose output structures include built-in registers and combinatorial or non-reg- 30 istered logic. The output signals of the registers are known as stored or registered signals or outputs, whereas the output signals of the combinatorial logic are known as non-stored or non-registered signals. Specifically, the combinatorial logic can be programmed to 35 provide non-inverted non-registered signals or inverted non-registered signals.
One disadvantage with the prior field-programmable logic families is that they have fixed numbers or combinations of registers and combinatorial logic gates. For 40 example, one logic sequencer may have four registers whose signal outputs are connected to four pins, respectively, and eight combinatorial logic gates whose signal outputs are connected to eight pins, respectively. Another logic sequencer may have six registers and a like 45 number of combinatorial logic gates whose signal outputs are connected, respectively, to twelve pins. However, a user or purchaser may need only three registers or five registers, thereby resulting in an inefficient or lack of use of register resources and pins since the pur- 50 chased logic sequencer will have four or six registers, respectively, connected to a like number of pins. In other words, a user or purchaser may not be able to utilize efficiently a logic sequencer with the exact number of registers and pins needed. Furthermore, a given 55 logic sequencer may not implement a given logic function should more registers be needed than are available on such a sequencer. Also, a user would need to purchase a variety of different logic sequencers to cover all applications, which increases inventory and production 60 costs.
Another disadvantage of the prior logic sequencers is that each register and each combinatorial logic gate is dedicated or coupled to a particular pin, respectively. This can present problems related to the lay-out of the 65 logic circuit on the chip. For example, it may be more space-saving or otherwise advantageous to have a given register laid out near an upper part of the chip, but the
dedicated nature of the chip to the user or purchaser may contrain the location of the given register near a pin at the middle or lower portion of the chip.
The present invention is directed to overcoming all of the problems mentioned above.
SUMMARY OF THE INVENTION
The present invention is an apparatus for producing an output signal at a single output, including means for providing a stored non-inverted first signal and a nonstored non-inverted second signal and or an inverted third signal of the first signal and an inverted fourth signal of the second signal, and means for selecting the first signal or the second signal or the third signal or the fourth signal for the output signal.
The four signals described above can be stored or registered signals and non-stored or non-registered signals, one of which is selected by the selecting means. A plurality of this apparatus can be implemented as output structures on a chip which are coupled to respective pins. A user can then individually cause the selecting means of any one apparatus to select any one of the four signals. Thus, for example, if only three registers are required, then three of these apparatus can be configured for providing the registered signals, either noninverted or inverted, with the remaining plurality of apparatus being configured for non-stored outputs, noninverted or inverted. Consequently, contrary to the prior art, the present invention provides maximum utilization of register and pin resources and design flexibility of configuring each output structure on a chip as needed and where needed.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates an integrated circuit package.
FIG. 2A and FIG. 2B are illustrations of prior art output structures.
FIG. 3 is a block diagram of one embodiment of the present invention.
FIG. 4 is a block diagram of a preferred embodiment of the present invention.
FIG. 5 is a block diagram of a modified form of the embodiment of FIG. 4.
DETAILED DESCRIPTION OF THE
FIG. 1 shows an integrated circuit package 10 having a plurality of pins 12. The particular package 10 that is shown is indicated as having twenty pins 12i-122o, although other packages can have different numbers of pins, such as a package having twenty-four pins. Package 10 has, for example, pins llz-Vls which can function as data input pins and pins 12i2-12j9 which can function as data output or bidirectional data input-output (I/O) pins.
Package 10 houses a chip 14 on which a logic circuit 16 is implemented. The architecture of chip 14 also includes a plurality of output structures 18 which receive inputs from the logic circuit 16 via lines shown generally at 20 and provide output signals on respective single outputs 22. As one example, there are eight respective output structures I812-I819 connected via respective single outputs 2212-2219 to respective pins 12i2-12i9.
FIG. 2A shows one type of prior output structure 18 and FIG. 2B illustrates another type of an output structure 18. FIG. 2A depicts combinatorial logic 24 and, in