Patent US5754803 - Parallel packetized intermodule arbitrated high speed control and data bus ...

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US005754803A

United States Patent [19] [ii] Patent Number: 5,754,803

Regis [45] Date of Patent: May 19, 1998

5,396,599 3/1995 Cobbs et al 395/280

5,398,243 3/1995 Aguihon et al 370/438

5,509,126 4/1996 Oprescuetal 395/307

5,561,669 10/1996 Lenney et al 370/352

FOREIGN PATENT DOCUMENTS

0022170A2 1/1981 European Pat. Off. H04L 5/00

0517609A1 12/1992 European Pat. Off. G06F 13/376

0525860A2 2/1993 European Pat. Off. G06F 13/28

2519443 7/1983 France G06F 9/40

Primary Examiner—Jack B. Harvey

Assistant Examiner—Sumati Lefkowitz

Attorney, Agent, or Firm—Volpe and Koenig, P.C.

[57] ABSTRACT

A parallel packetized intermodule arbitrated high speed control data bus system which allows high speed communications between microprocessor modules in a more complex digital processing environment The system features a simplified hardware architecture featuring fast FIFO queuing operating at 12.5 MHz, TTL CMOS compatible level clocking signals, single bus master arbitration, synchronous clocking, DMA, and unique module addressing for multiprocessor systems. The system includes a parallel data bus with sharing bus masters residing on each processing module decreeing the communication and data transfer protocols. Bus arbitration is performed over a dedicated serial arbitration line and each requesting module competes for access to the parallel data bus by placing the address of the requesting module on the arbitration line and monitoring the arbitration line for collisions.

20 Claims, 17 Drawing Sheets