(12) United States Patent (10) Patent No.: US 8,164,955 B2 Park (45) Date of Patent: Apr. 24, 2012 (54) NOR FLASH MEMORY DEVICE AND 55* %>1:1azfi1er}slg>v ml. ....... .. 257/314
METHOD FOR FABRICATING THE SAME
2004/0232444 A1 11/2004 Shimizu
FOREIGN PATENT DOCUMENTS
DE 19616603 A1 10/1996
EP 0657928 A1 6/1995
JP 07-221210 A 8/1995
JP 2003-282741 A 10/2003
KR 10-2002-0057341 7/2002
OTHER PUBLICATIONS
Kazerounian et al., “Alternate Metal Virtual Ground EPROM Array
Implemented in a 0.8um Process for Very High Density Applica-
tions,” Electron Device Meeting, 1991. IEDM ’ 91. Technical
Digest., International. pp. 311-314.*
Inoue et al., “NAND Flash Applicatoins Design Guide,” Apr. 2003,
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Office Action dated Oct. 4, 2011 in Japanese Application No. 2008-
208465, filed Aug. 13, 2008.
Primary Examiner * Alexander Sofocleous
(74) Attorney, Agent, or Firm * SaliWanchik, Lloyd &
Eisenschenk
Embodiments of a NOR flash memory and method for fabricating the same are provided. Bit lines can be formed as self-aligned source and drain regions betWeen adjacent first polysilicon patterns. Contacts for the source and drain regions can be provided according to bit line instead of per cell. Word lines can be formed as second polysilicon patterns, Which are used as control gates, and are provided perpendicular to the longitudinal axis of the bit lines. During formation of the second polysilicon patterns, a dielectric film and exposed regions of the first polysilicon patterns can be etched to form floating gates beloW the second polysilicon patterns.
6 Claims, 8 Drawing Sheets
