(12) United States Patent ao) Patent No.: us 6,356,500 Bi
Cloud et al. (45) Date of Patent: Mar. 12,2002
(54) REDUCED POWER DRAM DEVICE AND
METHOD
(75) Inventors: Eugene H. Cloud, Boise, ID (US); Kie
Y. Ahn, Chappaqua, NY (US); Leonard
Forbes; Paul A. Farrar, both of
Corvallis, OR (US); Kevin G.
Donohoe, Boise, ID (US); Alan R.
Reinberg, Westport, CT (US); David J.
Mcelroy, Livingston, TX (US); Luan
C. Tran, Meridian, ID (US); Joseph
Geusic, Berkeley Heights, NJ (US)
(73) Assignee: Micron Technology, Inc., Boise, ID
(US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 09/643,945
(22) Filed: Aug. 23, 2000
(51) Int. C I. G11C 7 00
(52) U.S. CI 365/226; 365/230.01; 365/240
(58) Field of Search 365/226, 229,
365/230.01, 236, 240
(56) References Cited
U.S. PATENT DOCUMENTS
5,493,574 A * 2/1996 McKinley 371/40.1
5,825,691 A * 10/1998 McClure 365/189.01
6,184,067 Bl * 2/2001 Casper 438/123
* cited by examiner
Primary Examiner—David Nelms
Assistant Examiner—-Thong Le
(74) Attorney, Agent, or Firm—Dickstein Shapiro Morin & Oshinsky LLP
(57) ABSTRACT
A memory device and method employing a scheme for reduced power consumption is disclosed. By dividing a memory array sector into memory sub arrays, the memory device can provide power to memory sub arrays that need to be powered up or, in the alternative, powered down. This reduces the power consumption and heat generation associated with high speed and high capacity memory devices.
39 Claims, 9 Drawing Sheets
