Semiconductor memory array of floating gate memory cells with buried ...

(54) SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH BURIED FLOATING GATE

(75) Inventors: Bomy Chen, Cupertino, CA (US);

Dana Lee, Santa Clara, CA (US); Hieu
Van Tran, San Jose, CA (US)

(73) Assignee: Silicon Storage Technology, Inc.,

Sunnyvale, CA (US)

( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.

(21) Appl. No.: 10/653,015

(22) Filed: Aug. 28, 2003

(65) Prior Publication Data

US 2005/0045940 Al Mar. 3, 2005

(51) Int. CI.7 H01L 29/788; H01L 21/8238

(52) U.S. CI 257/315; 257/314; 257/316;

257/317; 257/318; 438/201; 438/211; 438/257

(58) Field of Search 257/314-315,

257/316-318, 321-322, 331; 438/201, 211,

257, 266

FOREIGN PATENT DOCUMENTS

EP 0389721 10/1990

OTHER PUBLICATIONS

Hayashi, Fumihiko and Plummer, James D., "A Self-
Aligned Split-Gate Flash EEPROM Cell With 3-D Pillar
Structure", 1999 Symposium on VLSI Technology Digest of
Technical Papers, Center for Integrated System, Stanford
University, CA 94305, USA, pp. 87-88.
SZE, Simon, "Physics of Semiconductor Devices", 2nd
Edition, Wiley-Interscience, Basic Device Characteristics
pp. 438-439.

Brown, William D. et al.; "Nonvolatile Semiconductor Memory Technology, A Comprehensive Guide to Understanding And Using NVSM Devices", IEEE Press, pp. 33-34.

10/358,601, filed Feb. 2003, Kianian.
10/358,623, filed Feb. 2003, Hu et al.
10/757,830, filed Jan. 2004, Yeh et al.
10/105,741, filed Mar. 2002, Kianian.
10/776,397, filed Feb. 2004, Kianian et al.
10/776,483, filed Feb. 2004, Kianian et al.
10/818,590, filed Apr. 2004, Kianian et al.

Primary Examiner—Donghee Kang
(74) Attorney, Agent, or Firm—Gray
Freidenrich LLP

U.S. Appl. U.S. Appl. U.S. Appl. U.S. Appl. U.S. Appl. U.S. Appl. U.S. Appl.

No. No. No. No. No. No. No.

Cary Ware &

(Continued)

An array of floating gate memory cells, and a method of making same, where each pair of memory cells includes a pair of trenches formed into a surface of a semiconductor substrate, with a strip of the substrate disposed therebetween, a source region formed in the substrate strip, a pair of drain regions, a pair of channel regions each extending between the source region and one of the drain regions, a pair of floating gates each disposed in one of the trenches, and a pair of control gates. Each channel region has a first portion disposed in the substrate strip and extending along one of the trenches, a second portion extending underneath the one trench, a third portion extending along the one trench, and a fourth portion extending along the substrate surface and under one of the control gates.

36 Claims, 15 Drawing Sheets