[54] METHOD OF FORMING A
SEMICONDUCTOR DEVICE HAVING CMOS
STRUCTURES ON A SEMICONDUCTOR
SUBSTRATE
[75] Inventors: Michael D. Rostoker, San Jose;
Nicholas F. Pasch, Pacifica, both of
Calif.
[73] Assignee: LSI Logic Corporation, Milpitas,
Calif.
[21] Appl. No.: 571,345
[22] Filed: Dec 12,1995
Related U.S. Application Data
[63] Continuation of Ser. No. 278,573, Jul. 21, 1994, Pat. No. 5,514,616, which is a continuation of Ser. No. 33,213, Mar. 18,1993, abandoned, which is a continuation-in-part of Ser. No. 750,196, Aug. 26, 1991, Pat. No. 5,217,566.
[51] Int CI.6 H01L 21/70; H01L 27/00
[52] U.S. CI 438/210; 438/228; 438/229;
438/230; 438/233
[58] Field of Search 437/56, 34, 192,
437/52, 60, 47
[56] References Cited
U.S. PATENT DOCUMENTS 5,023,190 6/1991 Lee et al 437/56
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US005663086A [ii] Patent Number: 5,663,086 [45] Date of Patent: Sep. 2, 1997
5,342,802 8/1994 Kubokoya et al 437/57
5,478,761 12/1995 Komori et al 437/34
Primary Examiner—Jey Tsai
Attorney, Agent, or Firm—Oppenheimer, Poms, Smith [57] ABSTRACT
Methods of planarizing one or more layers having an irregular top surface topology in a semiconductor device based on an underlying MOS structure are disclosed. Methods of creating doped wells or regions for the underlying MOS structure are also disclosed, using thick oxide growths on the surface of the substrate to mask implantation of ions into the wells. A technique for creating a pair of adjacent complementary oppositely-doped wells, such as for a CMOS structure, using a thick oxide growths as a mask is also disclosed. One of the methods of planarizing the one or more layers involves depositing, densifying and re-flowing a layer of glass on top of the topological layer. Another method of planarizing the one or more layers involves depositing, densifying and chemical-mechanically polishing the deposited and densified glass, thereby avoiding an additional temperature cycle (i.e., for re-flowing the glass) which would adversely affect underlying diffusions.
61 Claims, 6 Drawing Sheets
