Node controller for performing cache coherence control and memory-shared ...

(54) NODE CONTROLLER FOR PERFORMING CACHE COHERENCE CONTROL AND MEMORY-SHARED MULTIPROCESSOR SYSTEM

(75) Inventors: Tsuyoshi Tanaka, Kokubunji (JP);

Hideya Akashi, Kunitachi (JP); Yuji
Tsushima, Kokubunji (JP); Keitaro
Uehara, Kokubunji (JP); Naoki
Hamanaka, Tokyo (JP); Toru Shonai,
Hachioji (JP)

(73) Assignee: Hitachi, Ltd., Tokyo (JP)

( * ) Notice: Subject to any disclaimer, the term ol this patent is extended or adjusted under 35 U.S.C. 154(b) by 647 days.

(21) Appl. No.: 09/585,390

(22) Filed: Jun. 2, 2000

(30) Foreign Application Priority Data

Jun. 3, 1999 (JP) 11-156560

(51) Int. CI.7 G06F 12/00

(52) U.S. CI 711/147; 711/141; 370/352

(58) Field of Search 370/352, 389;

711/202, 147, 141; 712/12

(56) References Cited

U.S. PATENT DOCUMENTS

5,165,038 A * 11/1992 Beard et al 711/147

5,560,027 A * 9/1996 Watson et al 712/12

5,933,857 A * 8/1999 Brewer et al 711/202

* cited by examiner

Primary Examiner—Gary Portka
Assistant Examiner—Thang Ho

(74) Attorney, Agent, or Firm—Mattingly Stanger & Malur, PC.

(57) ABSTRACT

In a multiprocessor system ol a main memory shared type having a plurality ol nodes connected each other through signal lines; each ol the plurality ol nodes includes CPUs having caches therein, a main memory, and a node controller for performing communication control between the CPUs, main memory and ones ol the nodes other than its own node. The node controller has a communication controller for controlling communication interlace between the plurality ol nodes, a crossbar lor determining a processing sequence ol memory access issued from at least one ol the plurality ol nodes to be directed to the main memories ol the plurality ol nodes, and crossbar controller for making valid or invalid the crossbar.

20 Claims, 15 Drawing Sheets