Error correcting code

1 ERROR CORRECTING CODE

FIELD OF THE INVENTION

The invention relates to an error correcting code, in particular to a method of generating the error correcting code, a method of calculating a parity symbol using the error correcting code and a method of using the error correcting code to correct an error in a received vector. The invention further relates to software for executing the method and to a system using the method.

BACKGROUND OF THE INVENTION

Error-correcting codes are well-known foruse in storage or transmission systems to be able to detect and correct at least one error that may have occurred during the storing/reading or transmission of a word. The word (infonnation symbol) typically includes a plurality of bits, e.g. 32 bits. One or more symbols are grouped together into a codeword. An error correcting code generates additional information that is usually referred to as a parity symbol(s). The entire code word (information symbols and parity symbol) is then stored/transmitted. Advanced error correcting codes are based on calculations in finite fields, such as Galois Fields (e.g. GF(2”)). A well-known error correction code is the Reed-Solomon code. Typically the codes are calculated before storing/transmitting and checked after reading/receiving using custom-designed hardware for executing the specific finite field calculations. In many applications a microcontroller or digital signal processor is available, however these processors usually do have hardware support for such operations. In itself it is known how finite field calculations can be perfonned using other operations of such conventional processors, often by table lookup. For most applications that is not practically possible since perfonning the conventional finite field calculations using integer operations requires too many processing cycles and is thus too slow. For low-cost applications the costs of the additional specific hardware is a problem.

SUMMARY OF THE INVENTION

It is an object of the invention to provide an error correcting code that is executable on an integer processing unit and is able to correct at least one q-ary symbol in a codeword, where q is an r’h power of two, ril, (q:2"). In particular it is an object to be able to correct an error in a 4-ary symbol (q:22) for a 4-level memory cell such as, for example, is often used in a NAND memory.

To meet the object of the invention a method is provided of generating an error correcting1code for correcting at least one q-ary symbol, where q is an rt power of two, ri 1, (q:2'); the method includes:

using as the error correcting code a code word u that includes k information symbols u[0], . . . , u[k—1]; k>1 and a parity symbol u[k] for protecting the information symbols (for example, u:(u[0], . . . ,u[k—1],u[k])); each infonnation symbol representing an integer in the range {0, . . . , 2W—1}, where w:n*r, ni 1 ;

including in the parity symbol u[k] a term —(a[0]~u[0]+a [1]~u[1]+ . . . +a[k—1]~u[k—1]) mod M, where MZ2n(k+1)(q— 1)+1, where the multiplication ~ and the addition + are integer operations executable by an integer processing unit and where a[0], . . . , a[k—1] are constants in {0, . . . , M—1}; and

choosing the constants a[0], . . . , a[k—1] such that the elements a[i]~d~q7 mod M are unique for ie{0, . . . , k—1},je {0, . . . ,n—1}, —q<d<q, d==0.

To meet the object of the invention a system is provided for protecting a codeword u against an error in at least one q-ary symbol, where q is an r-power of two, ril (q:2"), the system including:

2

means for receiving the code word u including infonnation symbols u[0], . . . , u[k—1], k>1, each information symbol representing an integer in the range {0, . . . , 2W—1}, where w:n*r, ni 1 ;

a processor including an integer processing unit for, under control of a program, calculating a parity symbol u[k] for protecting the infonnation symbols, where the parity symbol includes —(a[0] ~u[0]+a[1]~u[1]+ . . . +a[k—1]~u[k—1]) mod M, where MZ2n(k+1) (q—1)+1, where the multiplication ~ and the addition + are integer operations and where a[0], . . . , a[k—1] are constants in {O . . . , M—1} chosen such that the elements a[i]~d~q7 mod M are unique for ie{0, . . . , k—1}, je{0, . . . , n—1}, —q<d<q, d==0; and

means for adding the parity symbol u[k] to the codeword u before transmitting or storing the codeword.

The code can correct one or more q-ary symbol errors and uses only integer operations (addition, multiplication and modulus). As such the code can be easily executed on conventional integer hardware. Only a few cycles are required, making the code also fast.

It should be noted that codes that are defined by a linear congruence similar to the described relationship are known in the literature as Varshamov-Tenengolts codes (1965) described in R. R. Varsharnov: “A class of codes for asymmetric channels and a problem from the additive theory of numbers”. IEEE Transactions on Infonnation Theory, Vol. IT-19, No. 1, January 1973. The codes have been studied with respect to their capacity of correcting asymmetric errors (e.g. “O” may be mapped into “1” but not vice versa). It is further noted that Levenshtein has observed that these codes have properties for correcting insertions and deletions, too. However, these codes have not been considered for correcting q-ary-symbol errors due to their poor distance properties. The claimed code further deviates in that the information symbols may exceed the range specified by the modulus M (2WZM).

According to the measure of the dependent claim 2, a table is formed that enables, for each single error in a q-ary symbol in a received vector, retrieval of infonnation that indicates which q-ary symbol is corrupted and how it can be corrected. Using such table makes the execution fast. The table may be stored in low-cost memory, e.g. ROM.

As defined by the measure of the dependent claim 3, the modulus M is preferably chosen as the largest prime in the allowed range. This simplifies choosing suitable constants.

As defined by the measure of the dependent claim 4, suitable constants can be found by iteratively selecting and testing randomly chosen values.

As defined by the measure of the dependent claim 5, an effort is made to chose small constants that meet the requirement. Using small constants (e.g. 8-bit values) increases the processing speed on simple processors.

These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

FIG. 1 shows a block diagram of an embodiment according to the invention;

FIG. 2 illustrates the processing steps according to the invention; and

FIG. 3 provides more details on the structure of the data.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 shows a block diagram of an embodiment of a system 100 according to the invention. In this embodiment, the system includes a processor 130 that performs the core